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March 24, 2009

Mtg: Through-Silicon Vias (TSVs): Design and Reliability

by @ 1:44 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Semiconductors

WEDNESDAY May 13, 2009
SCV Components, Packaging & Manufacturing Technology Chapter, with Electron Devices and Circuits & Systems
Speaker: Sergey Savastiouk, ALLVIA, Inc.
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by April 6; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website

Thinned wafers with through-silicon isolated metal vias (TSVs) open a valuable new design opportunity for both IC and package engineers.? Through-silicon metal connectivity enables electrical and thermal performance advantages, back-side connectivity for two-sided semiconductor wafer and chip-level testing, as well as vertical interconnections for 3D IC stacking and micro- and opto-electronics.
The benefit of IC vertical interconnects such as TSVs has been presented in many papers.? The term TSV was introduced by the presenter in 1996 and published in 2000.? However, the physical design and reliability issues associated with copper through-silicon vias have not been fully resolved.? The following problems present process challenges: metal voiding during filling, uniform via wall material deposition, and active IC surface connectivity to name a few.
Copper vias fabricated in a silicon wafer impose, at high temperatures, tensile stresses in silicon.? The situation might be aggravated by the stress fields due to numerous vias and, if the vias are placed too close to each other, the thermally induced stresses might lead to cracking of the silicon wafer.? In addition, the vias experience compressive ‘hoop’ stresses.? These stresses could lead to the via buckling.
The presentation will address other design and reliability issues.

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