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April 21, 2009

Mtg: Wafer-Level Packaging â?? Next Turn in the Road

by @ 4:00 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors
 

WEDNESDAY June 10, 2009
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Dr. Thomas Di Stefano
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by June 8; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website
Web: www.cpmt.org/scv

Wafer Level Packaging has long been the promised land of semiconductor manufacturing, but to many it seems we are still in the wilderness.? The promise is as attractive as ever and even more so in an economic environment where continuous cost reduction dictates rationalization of back-end packaging and test.? Until now, Wafer Level Packaging has proceeded slowly into larger, high-value devices where a reliable die attach technology is an ongoing issue.? Presently, several DRAM manufacturers are readying Wafer Level or Through Silicon Via packaging for production.? This next leg upward will require cost-effective infrastructure for burn-in, test and handling.? The methods, tools and standards necessary for growth of this supporting infrastructure represent both a problem and an opportunity.? It is not at all clear which of several alternative paradigms will win, but one thing is sure — the back-end infrastructure needs attention and coordinated effort, and perhaps new paradigms for solving long-standing problems known earlier under the rubric “KGD”.

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