IEEE Bombay Section

Past Events

Thursday, 21st December, 2006 , 1130 hrs
"An Overview of FLASH-OFDM and other Mobile Broadband Technologies"
by Dr. Samir Kapoor, Senior Director, Engineering, QUALCOMM Inc
Venue: Seminar Hall, EE Dept., IIT ,Powai , Mumbai
Jointly with Jointly with COMMSOC Chapter and IIT Bombay
Dec 18-20, 2006 Conference on Electric & Hybrid Vehicles, Pune, India
Jointly organised by IES/PAS Chapter and Pune Subsection of IEEE Bombay

Friday, 10th November, 2006 , 1400-1600 hrs
"Modelling decanometer devices: Challenges and Perspectives"
by Prof. E. Sangiorgi, Univ. of Bologna, Italy
Venue: Institute Auditorium, IIT ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Friday, 10th November, 2006 , 1000-1200 hrs
"Advanced SOI Technology : materials, devices,and mechanisms"
by Prof. E. Cristoloveanu, Grenoble, France
Venue: Institute Auditorium, IIT ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Wednesday, 23rd August , 2006 , 1430 hrs
"Inertial MEMS sensors"
by Prof. S. A. Gangal, University of Pune
Venue: Nanoelectronics Conference Room, 2nd floor, EE (Annex) Bldg., I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Tuesday, 15th August , 2006 , 1600 hrs
"What can Self-assembled Monolayers (SAMs) do for MEMS/NEMS?"
by Dr. K.P. Vijayamohanan, Group Leader, Materials Electrochemistry Group,National Chemical Laboratory (NCL), Pune
Venue: Nanoelectronics Conference Room, 2nd floor, EE (Annex) Bldg., I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Tuesday, 8th August , 2006 , 1530 hrs
"Ubiquitous Multimedia Computing and Communication: Challenges and Future Trends"
by Professor C. -C. Jay Kuo,University of Southern California
Venue: EE Seminar Hall, I.I.T. ,Powai , Mumbai
Jointly with IEEE Communications Society and IIT Bombay
Thursday, 3rd August , 2006 , 1430 hrs
"Power Semiconductor Device Technology An Overview"
by Dr. Ritu Sodhi, International Rectifier
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Wednesday, 2nd August , 2006 , 1400 hrs
"GaN based optoelectronic materials and devices"
by Dr. Arnab Bhattacharya, Dept. of Condensed Matter Physics and Materials Science,Tata Institute of Fundamental Research, Mumbai
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Tuesday, 18th July, 2006 , 1700 hrs
"Advanced Electronic Systems Engineering"
by Professor Krishna Shenai, FIEEE ,USTAR Professor, Utah State University,Logan,UT,USA
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Thursday, 22nd June, 2006 , 1000 hrs
"System of Systems and current developments in Aerospace Technology"
by Dr Zafar Taqvi, NASA, USA
Venue: Aerospace Seminar Room, I.I.T. ,Powai , Mumbai
Jointly with Aerospace Dept, IIT Bombay
Monday, 12th June, 2006 , 1100 hrs
"Nano and Micro Structures, Processes and Packaging for Advanced Integrated Sstems: Research, Education and Enterpreneurship"
by Ajay P. Malshe, Ph.D., FInstP, Faculty of Electrical Engineering and Microelectronics and Photonics, University of Arkansas
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
April 26-27, 2006
Visit of IEEE President Dr Michael Lightner to Bombay Section
Presentation by Dr Lightner and meeting with Section at RBYC on April 26.
March 24-25, 2006 "2nd Workshop on Design Verification Methodologies" Venue – Wipro Technologies, Pune, India
Saturday 18th Feb 2006 , "Year 2006 Prof K Shankar Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
The last date for Submitting the papers and Project ideas : 6th February 2006
The date of presentation of the selected papers and projects : 25th February 2006.
The authors of the selected papers will be intimated of the selection by 8th February 2006.
Saturday 18th Feb 2006, "Communications Society Chapter Student Project Contest"
Friday, 10th February, 2006 , 1600 hrs
"Novel Tunneling Devices for Future CMOS Technologies"
by Dr.Krishna K Bhuwalka, Institute of Physics, Universität der Bundeswehr Munich
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Monday, 16th January, 2006 , 1430 hrs
"Impact of technology on sub 90 nm VLSI circuits"
by Dr. Rajiv V. Joshi, Research staff member at T. J. Watson research center, IBM
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
Thursday, 22nd December, 2005 , 1500 hrs
"ENTROPIC MODELING OF THERMOELASTIC DISSIPATION IN MICROSTRUCTURES "
by Mr. Saurabh A. Chandorkar
Venue: EE Conference Room, I.I.T. ,Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay
19th - 21st December, 2005
"Micro Electronics and VLSL conference IINC2005"
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay http://www.ee.iitb.ac.in/~imaps "Detail of IINC2005"

"Annual General Body Meeting"... Notice...Saturday 17th December 2005
- Slate given by Nominations Committee
- Minutes of last AGM
- Events in 2005
- Secretary Report
Wednesday, 14th December,2005, 1100 hrs
"Distributed Kernel Regression : An Algorithm for Training Collaboratively"
by Joel B. Predd Information Sciences and Systems Group, Princeton University
Venue: EE Conference Room, 1st Floor, Opp. Old EE Office , I.I.T. , Powai , Mumbai
Jointly with COMSOC Chapter and IIT Bombay

Tuesday, 13th December,2005, 1100 hrs
"The First Ten Years of Automotive Telematics"
by Dr. K. Venkatesh Prasad, Ford Research & Advanced Engineering, Ford Motor Company, Dearborn, Michigan, USA
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay

Monday, 12th December, 2005,1530 hrs
"Looking in and Looking out of an Automobile: Computer Vision for Safer Driving"
by Prof. Mohan M. Trivedi, University of California at San Diego
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay

Monday, 12th December,2005, 1100 hrs
"THE DIGITAL ALLPASS FILTER : A VERSATILE SIGNAL PROCESSING BUILDING BLOCK"
by Dr. Sanjit K. Mitra Department of Electrical & Computer Engineering University of California, Santa Barbara, California
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay

December 11-13 , 2006 "M.V.CHAUHAN STUDENTS’ PAPER CONTEST 2005"
Friday, 2nd December, 2005,1530 hrs
"Mastek's experiences in the implementation of London Metro Transport Project"
by Shri. Ashank Desai, Chairman of Mastek
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with COMSOC chapter, Gold members and IIT Bombay

Monday, 28th November, 2005,1500 hrs
"Device Modeling - The art of making approximations"
by Dr. Shreepad Karamalkar, Professor of Electrical Engineering,Indian Institute of Technology (IIT) Madras
Venue: EE Conference Room , I.I.T. , Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay

Thursday, 24th November,2005, 1500 hrs
"Non-Invasive and Blood-Free Diabetic Monitoring Using Novel Transdermal Patch Technologies"
by Prof. M. Paranjape, GAEL Health Microsystems and the Dept. of Physics Georgetown University, Washington D.C. USA
Venue: EE Conference Room, 1st Floor, Opp. Old EE Office , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay

Monday, 31st October,2005, 1600-1800 hrs
"INFORMATION AND COMMUNICATIONS TECHNOLOGIES A PRIORITY FOR AFRICA'S SELF - DEVELOPMENT"
by Dickson Ochola Oming'o Chief Lecturer and Head, Department of Electrical & Electronics Engineering Kenya college of Communications Technology NAIROBI, Kenya
Venue: Conference Hall, 15th floor, MTNL Telephone House, Prabhadevi, Mumbai - 28
Jointly with Comsoc Chapter and IETE Mumbai Centre

Wednesday, 19th October,2005, 1730 hrs
"Film - 50 years in 50 minutes"
Venue: EE Conference Room, 1st Floor, Opp. Old EE Office , I.I.T. , Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay

Saturday, 8th October,2005, 1100 hrs
"WIRELESS BASED ICT FOR DEVELOPMENT : ICTP EXPERIENCE AND FUTURE PLANS"
Dr Sandro Radicella, Professor and Head, ARPL Laboratory, The Abdus Salam International Centre for Theoretical Physics, Italy
Venue: Mini Auditorium, SNDT University, Juhu Road, Santacruz (W), Mumbai-49
Jointly with Comsoc Chapter and IIT Bombay

Friday, 30th September,2005, 1500 hrs
"Understanding the Impact of Surface Engineering, Structure, and Design on Electromigration through Monte Carlo Simulation and In-Situ SEM Studies"
by S. G. Mhaisalkar, School of Materials Science & Engineering, NTU, Nanyang Avenue, Singapore 639798
Venue: EE Conference Room, 1st Floor, I.I.T. , Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay

Friday, 12th August,2005, 1530 hrs
"Network Coding: Mixin' it up"
by Sidharth Jaggi, Department of Electrical Engineering California Institute of Technology, U.S.A.
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay

Thursday, 11th August,2005, 1530 hrs
"Engineering Complex SoCs Using Configurable Microprocessor Cores"
by Himanshu A. Sanghavi
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with AP/ED Chapter and IIT Bombay

Aug 20-21 , 2005 "All India Student's Congress - Innovations in Technology"
Friday, 5th August, 2005, 1700 hrs
"Gas Insulated Substations (GIS) and Gas Insulated Transmission Lines (GIL)"
by :Dr Herman Koch, a DL from Siemens, Germany
Venue: MSEB Hall in Bandra
Jointly with IEEE PES Bombay Chapter and MSEB
About the Speaker: Dr.-Ing. Hermann Koch was born in November 1954 in Hauswurz, Germany. In 1979 he graduated in Industrial Control Engineering at the Fachhochschule Rüssels¬heim. From 1980-1981 he studied at New Jersey Institute of Tech¬nology, Newark, New Jersey, USA. 1986 he graduated in Electrical Engineering at the Techni¬cal Uni¬versity of Darmstadt. He received his Dr.-Ing. degree in 1990 from the Technical University of Darmstadt at the High Voltage Institute. From 1990 to 2004 he was working with Siemens High Voltage Division where he was head of Gas Insu¬lated Lines De¬partment. Since 2004 he is responsible for the business development of Siemens Power Technology. He is secretary of the IEEE PES Sub¬stations Committee. In the IEC he is secretary of SC 17C for GIS/GIL, in CENELEC he is Secretary of TC 17 for GIS/GIL, and he is member of CIGRE B3 Substation Committee.
Activities in IEEE PES:
since 1994 Active member of the Substation GIS Subcommittee, participating in K0, K1, K2, K3, K4
1996-2000 Active member of the Substation Environmental Subcommittee G0 and G2
since 2002 Chairman of Substation GIS Subcommittee
Contributions in the field of GIS and GIL at the following PES Meetings: Summer Power Meetings 2001, 2002, Winter Power Meetings 2001, 2002, ICC Fall Meeting 2000, Transactions on Power Delivery 2000, and General Meeting 2003.
Organisation of Panel Discussions on Gas-Insulated Transmission Lines (GIL) 2000 at the Summer Meeting and upcoming in 2003 at the General Meeting.
Preparation of a tutorial on Gas-Insulated Substations (GIS) and Gas-Insulated Transmission Lines (GIL) to be held first at the Substation Meeting 2003 and the T&D Exhibition and Conference in 2003.
Thursday, 14th July, 2005, 1530 hrs
"An Overview of the Problems of Radiation from Antennas with Emphasis on Microwave Frequencies"
by : Prof. B. N. Das
Venue: Conference Room 2nd Floor, Sameer Main Bldg. SAMEER, IIT Mumbai Campus
Jointly with IEEE AP/ED Bombay Chapter and SAMEER
About the Speaker: Prof.B.N Das is an Emeritus Professor in ECE & Department of INDIAN INSTITUTE OF TECHNOLOGY,KHARAGPUR. He has made Outstanding contributions in the areas of Antennas and Propagation . He is well known for his lifetime achievements in this field and as an outstanding Teacher and Educator
Tuesday, 12th July, 2005, 1100 hrs
"NanoCAD: Computer-Aided Design Algorithms and Tools for Nanotechnologies"
by : Prof. Niraj K. Jha, Dept. of Electrical Engineering, Princeton University
Venue: EE Seminar Hall, IIT Powai
Jointly with IEEE AP/ED Bombay Chapter and IIT Mumbai

Friday, June 24, 2005, 1430 to 1800 hrs
"1. The Art & Science of Software Process
2. Software Development Challenges for the 21st Century "
by : Mr Steven Teleki, Director, Software Development, Webify Solutions, Inc. and Past Chairman of the IEEE Computer Society, Austin Chapter, Texas, USA.
Venue: Gateway Park, 6th floor Conference Room
Jointly with Computer Chapter and TCS
Abstract: Increasing the productivity of knowledge work and of the knowledge worker are the factors that will make the people, teams, and companies lead during the 21st century. For software professionals, understanding productivity starts with an understanding of what a professional actually does to create software. Listen to Steve Teleki challenge your basic assumptions about how software work is done today and leave with specific ideas that you can implement in your own work. You will leave feeling compelled to take action to stand out from the crowd and become a leader in today’s software business. About the Speaker: Steven Teleki is a software development manager & mentor. He is Software Development Director at Webify Solutions, Inc., a company offering Insurance On Demand and Healthcare On Demand solutions that deliver measurable business outcomes to its Clients. Steve has over 18 years of experience in the software industry; has worked on software that was released to over 40 million customers worldwide; has 3 software patents. He is passionate about solving problems with great software on a schedule and budget that makes the project successful. He focuses on understanding, measuring, and improving individual, team, and organizational software development performance. Contact him at teleki@computer.org.
You can see the slides at this page:
http://pseng.net/speaking/
You can also find his bio and the summary of the SD Challenges talk here:
http://ewh.ieee.org/r5/central_texas/austin_cs/presentations/2005-04-19.html
Thursday, 16th June, 2005, 1500 to 1900 hrs
"Half Day Seminar on "Grooming and Survivability in Optical Networks"
by : Dr Arun K. Somani, Jerry R. Junkins Chair Professor and Chair Electrical and Computer Engineering, Iowa State University, USA
Venue: MTNL, Conference Room, 15th Floor, Telephone House, Prabhadevi, Mumbai 400028
Jointly with COMSOC Chapater and IETE Mumbai Centre
Abstract: We addresses the need and issues in WDM networks with traffic grooming capabilities, supporting lower-rate circuit-switched traffic streams. Traffic grooming in WDM networks, is defined as the act of multiplexing, demultiplexing and switching lower rate traffic streams onto higher capacity lightpaths. In such a network, in addition to add/drop and full wavelength switching features, some or all of the network nodes can be provided with the capability to switch lower-rate traffic streams from one wavelength on an input port to another wavelength on an output port. We will also discuss restoration algorithm to maintain high performance and reliability. A new architecture, called Light Trails, being implemented at ISU that deploys switch-less traffic grooming for LAN and MAN applications will also be described
Tuesday, 7th June, 2005, 1100 hrs
"Semiconductor/Ferromagnet hybrid deveces for Spintronics"
by Tamalika Banerjee MESA+ Institute for Nanotechnology University of Twente The Netherlands
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter and IIT Bombay
Abstract: In this talk, a brief introduction to the field of Spintonics and its potential with particular relevance to the existing applications will be given. Thereafter, I shall discuss an interesting class of hybrid devices (Semiconductor/ferromagnet) like the Spin-Valve Transistor and the Magnetic Tunnel Transistor, which are based on the spin dependent transport of non-equilibrium carriers. Important device characteristics and performance, and the underlying physics essential for the operation of such devices will also be discussed. Finally, our recent results on the first observation of spin filtering of hot holes in a similar system using the technique of Ballistic Hole emission Microscopy will be presented.
About the Speaker Dr (Ms) Tamalika Banerjee did M.Sc. at University of Calcutta and Ph.D. at University of Madras in the year 2000. Her Ph.D. work was on Oxygen irradiation effects in Pb and Pb-Sn doped Bi-2223 superconductors, for which she extensively used the accelerator facilities at Nuclear Science Centre, New Delhi and obtained the Best Thesis Award from Indian Physics Association in December 1999. In May 2000, she joined Tata Institute of Fundamental Research (TIFR) as a Post Doctoral Fellow to work on Vortex dynamics in superconductor thin films at microwave frequencies. Here, she was a member of the team which observed for the first time the Peak Effect (PE) phenomenon in laser ablated DyBa2Cu3O7-d and YBa2Cu3O7-d thin films at microwave frequencies, and contributed significantly in the understanding of the PE phenomenon.
Although Dr. Banerjee had carried out some work on Spin-injection in superconductor-ferromagnet heterostructures while at TIFR, her major contribution in Spin-electronics or Spintronics during the last 3 years is at MESA+ Institute of Nano technology, University of Twente, The Netherlands where she is currently working. MESA+ Institute is an important centre for Spintronics where the first Spin Valve Transistor (SVT) was invented in 1995. Although Spintronics has a high potential, its eventual success will depend upon the coexistence of silicon device unit processes with the ferromagnetic layers. Dr. Banerjee has made significant contributions in areas such as SVTs, Magnetic Tunnel Transistors (MTTs) and the recent work on the first observation of spin filtering of hot holes using the technique of Ballistic Hole Emission Microscopy.
Monday, 6th June, 2005, 1700 hrs
"Packet Aware Transport for Metro Networks"
by Dr KK Ramakrishnan, Technology Leader at AT&T Labs.- Research, USA
Venue: Central Railway Auditorium, 4th Floor Parcel Office Building CST, Mumbai
Jointly with COMSOC Chapater , IETE Mumbai Centre, IRSTE

Thursday, 2nd June, 2005, 1600 hrs
"RF-MEMS"
by Dr. Sayanu Pamidighantam, BEL
Venue: EE Conference Room, I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter and IIT Bombay
Abstract: MEMS group of Bharat Electronics Limited (BEL) has been involved in the development of pressure sensor, gas sensor, accelerometer and RF-MEMS components. In this talk an overview of the MEMS activities at BEL, Bangalore is described. Followed by some detailed presentation on RF-MEMS. First results on RF-MEMS devices such as switch, inductor, and capacitor (first of its kind in India) will be shown. Future directions will also be covered to some extent.
About the Speaker Dr. Sayanu Pamidighantam has been working in BEL, Bangalore since Jan 2005 as Deputy Manager. Prior to joining BEL, he worked at IISC, Bangalore as Research Associate for two years. He obtained his Ph.D degree in the area of RF-MEMS from IMEC/Katholieke University, Leuven, Belgium in March 2004. In addition to his academic exposure, he also had an industry experience for two years in Singapore in a state of the art CMOS wafer foundry. Sayanu has published about 13 publications in International conferences and journals. Most recent was his contribution to Encyclopedia of Sensors.
Wednesday, 1st June, 2005, 1500 hrs
"Fabrication and Characterization of GaN Transistors and Schottky diodes"
by Dr. Vinayak Tilak, GE Global Research, Niskayuna, NY
Venue: EE Conference Room, I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter and IIT Bombay
Abstract: Gallium Nitride based transistors have emerged as an exciting candidate for high power RF applications. The physical constants of gallium nitride, like wide band gap (3.4 eV), high saturation velocity (2.8E7 cm/s), high breakdown field ( > 3 MV/cm) and the spontaneous polarization gives it an inherent advantage compared to other material systems like Silicon or Gallium Arsenide for high power applications. Heterostructure field effect transistors were fabricated on AlGaN/GaN heterostructures grown both on sapphire and silicon carbide substrates. Typical DC currents measured was over 1 amp/mm and transconductance over 250 mS/mm. Small signal measurements on a device with 0.3 micron gate length gave Ft of 33 GHz.RF power was measured at 10 GHz, and a 100 micron periphery device ouput a saturated power density of 11.7 W/mm. This is ten times higher power density than on Gallium Arsenide based transistors at this frequency. To achieve high RF power densities, the sample needs to be passivated using PECVD silicon nitride. A 1.5 mm device was fabricated, which output a saturated power density of 5.6 W/mm at 10 GHz. We shall discuss the trade offs involved in scaling the device to achieve high power densities seen in small periphery devices. Another potential application of Gallium Nitride based devices is in the field of harsh environment sensors. Pt based Schottky diodes were fabricated on 1X1017 cm-3 n doped GaN. These devices were exposed to hydrogen to temperatures upto 365C. The devices showed sensitivity to hydrogen and the sensitivity was found to be diffusion limited.
About the Speaker Vinayak Tilak was born in Chennai, India. He recieved M.Sc in Physics and B.E. Electrical Engineering from Birla Institute of Technology and Science, Pilani in 1997. and his PhD in Applied and Engineering Physics from Cornell University, Ithaca, N.Y in 2002. He is currently a member of technical staff at GE Global research at Niskayuna, NY. He has authored or Co-authored more than twenty publications and filed four patents. His research interests include wide band gap devices in applications ranging from microwave devices to sensors. He is a member of IEEE and MRS societies.
Tuesday, 12th April, 2005, 1200 hrs
"SeriesResistance Reduction in FinFETs using S/D Engineering"
by Mr. Abhisek Dixit IMEC ,Belgium
Venue: EE Conference Room, I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter and IIT Bombay

Saturday 2nd April 2005 , "Year 2005 Prof K Shankar Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
Wednesday, 23rd March 2005, 1600 hrs IEEE ED Distinguished Lecture
"Manufacturing of Nanosystems and Microsystems: Challenges and Opportunities"
by Prof. Rajendra Singh, Fellow IEEE, D. Houser Bank Professor of Electrical Engineering, Clemson University, USA
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter
Thursday, 17th March, 2005, 1630 hrs IEEE IAS Distinguished Lecture
"Understanding the Impact of Power Quality on Industrial Processes"
by Prof. Deepak Divan (Fellow, IEEE), Georgia Institute of Technology, USA.
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE IAS Bombay Chapter
Abstract: The availability of secure, reliable and high quality electric power is critical for meeting the needs of a modern industrial economy. Maintaining the availability of reliable and cost-effective electricity in the face of increasing congestion, an aging power delivery infrastructure and mushrooming energy consumption, poses a technical, regulatory and financial challenge. Improving the utilization of existing assets can unlock the value that is trapped in the T&D infrastructure. Active power flow control, VAR compensation and grid-monitoring are key technologies that can dramatically improve grid utilization, while improving system reliability. The second, possibly more important impact, especially for high-tech manufacturers, is power quality, and the unscheduled downtime that results from power disturbances occurring on the grid. This presentation will also look at the impact of the various types of power disturbances on typical industrial equipment and processes. Based on the underlying phenomenon associated with power disturbances, and on actual data measured across hundreds of industrial installations, a strategy is presented for understanding and then finding a solution for the problem of unscheduled downtime. Different types of solutions are discussed including UPS, voltage sag compensators, active filters and ride-through devices for application at a plant, bus or machine level. Industry standards from organizations such as SEMI, IEEE, ITIC and IEC are also discussed. Case studies from various manufacturing sectors, including semiconductors, automotive, food, plastics and fiber optics, show how the problems were identified and resolved.
National Seminar - IT the Change Agent, 10 -11 March 2005, Mumbai

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Friday, 4th March 2005,1730 hrs
"Electron transport in Si and its quantum heterostructures"
by Prof. P. K. Basu, Institute of Radio Physics and Electronics, University of Calcutta
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter
Abstract: Study of fundamental electronic properties in material Si: the most important material in modern VLSI circuits, stands in its own merit. Electron mobility under ohmic and high field condition is an important physical parameter, the knowledge of which is needed in device modeling. With downsizing of basic FETs, new phenomena like quantization of electron motion, tunneling, hot electron injection etc. creep in and they require thorough investigation. Furthermore, alternative technologies like SiGe/Si heterojunctions, SiC, are being introduced to realize better digital and analog devices and study of basic processes in them is assuming importance. In the present talk, the transport phenomena in silicon and its alloys and quantum heterostructures will be described and the methods of analyzing the data will be described. The strain induced band gap engineering and mobility enhancement will also be mentioned. The knowledge acquired from the studies will be applied to investigate the performance of newer Si based photonic devices, like Quantum Cascade Lasers, QWIPs, already developed using compound semiconductors.
Friday, 4th March 2005,1430 hrs
" A New Understanding of Electromigration Induced Void Nucleation, Growth, and Movement in Cu Interconnects"
by S. G. Mhaisalkar, School of Materials Science & Engineering, Nanyang Technological University, Nanyang Avenue, Singapore
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter
Abstract: In sub-micron damascene Cu interconnects, the dominant role of interfacial diffusion at the Cu/dielectric cap interface is widely accepted.Thus the role of the interfacial structure, composition, adhesion, is expected to play a significant role in determining the electromigration lifetime of the advanced interconnects. However, the inter-relationship of all these factors, materials, processes, and the dual damascene architecture on the void nucleation, growth, and eventual failure is still far from understood. In this study the effect of reducing, inert, and reactive gas treatments so as to induce compositional changes at the interface as well as different cap layers including silicon carbides, nitrides and their variants were studied. Upper and lower level test structures were subjected to different treatments after CMP and the electromigration performance was assessed on the package level. In untreated samples, the asymmetry of the test structures leads to higher MTFs for the upper layer test structures; however it was determined that upon surface treatments, the MTFs of lower layer test structures showed a 2x improvement and could achieve lifetimes comparable to the upper layer test structures. The role of the interfacial composition and microstructure on this improvement was studied through TEM and XPS and the role of interfacial adhesion was studied using four point adhesion tests and nano scratch tests. In order to completely characterize the effect of the interface on electromigration and to determine the nature of void nucleation, growth, and void migration; in-situ SEM electromigration experiments were carried out and the observed results indicate that the void formation is controlled through heterogeneous nucleation at the interface.
About the Speaker Bio: Associate Professor Subodh Mhaisalkar, has over 10 years of experience in senior R&D and Process Engineering positions in the field of microelectronics. He has held positions of Director of Engineering in ST Assembly & Test Services and senior managerial positions in National Semiconductor and Singapore Institute of Manufacturing Technology (SIMTech). Prof. Subodh's area of expertise has been reliability, process engineering, packaging design and development of advanced electronic materials and has in his career in the industry has pioneered design, process, thermal management, and design elements for packaging of microprocessors, flip chip assemblies, plastic packages, and advanced ball grid arrays. Subodh received his Bachelor's degree from IIT Bombay (Metallurgical Engineering), and Masters and PhD degrees from The Ohio State University (Materials Science & Engineering). His current research interests include organic thin film transistors, photovoltaics, memory devices; and nanoelectronics materials, processes, packaging, and reliability.
Thursday, 3rd March 2005,1500 hrs
"Nonlinear and fluid results for experiments with nano-oscillators"
by Dr. Rustom Bhiladvala, The Pennsylvania State University
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter
Abstract: This talk will focus on results from the measurement of resonance in structures at micron and nanometer scales. Due to their size, such small resonant structures have the potential for commercial instruments with sensitivities high enough for unprecedented sensing applications, such as the detection of pathogens and biomolecules, and well resolved measurement of gradients of fluid properties. We will look at two types of structures: paddle-beam oscillators made by conventional micromachining and nanowires, which are grown off-chip and can be surface-treated in batches before assembly, for versatility in sensing applications. Experiments with a paddle beam oscillator showing both nonlinear softening and stiffening are understood through a nonlinear oscillator model with coefficients dependent on thermal stress. Results for beam oscillator behaviour in a gaseous environment in continuum, free molecular and transition regimes and an open problem of unsteady flow in the transition regime will be presented.
Thursday, 24th February, 2005, 1130 to 1230 hrs
"Some Techniques for Performance Enhancement of Microstrip Patch Antennas using Metamaterials as Substrates and Superstrates"
by Dr. Raj Mittra, Professor of Electrical Engineering The Pennsylvania State University, University Park, PA 16802
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter
About the Speaker Raj Mittra is Professor in the Electrical Engineering department of the Pennsylvania State University. He is also the Director of the Electromagnetic Communication Laboratory, which is affiliated with the Communication and Space Sciences Laboratory of the EE Department. Prior to joining Penn State he was a Professor in Electrical and Computer Engineering at the University of Illinois in Urbana Champaign. He is a Life Fellow of the IEEE, a Past-President of AP-S, and he has served as the Editor of the Transactions of the Antennas and Propagation Society. He won the Guggenheim Fellowship Award in 1965, the IEEE Centennial Medal in 1984, the IEEE Millennium medal in 2000, the IEEE/AP-S Distinguished Achievement Award in 2002 and the AP-S Chen-To Tai Distinguished Educator Award in 2004. He has been a Visiting Professor at Oxford University, Oxford, England and at the Technical University of Denmark, Lyngby, Denmark. He has also served as the North American editor of the journal AE.
He is the President of RM Associates, which is a consulting organization that provides services to industrial and governmental organizations, both in the U. S. and abroad.
His professional interests include the areas of Communication Antenna Design, RF circuits, computational electromagnetics, electromagnetic modeling and simulation of electronic packages, EMC analysis, radar scattering, frequency selective surfaces, microwavand millimeter wave integrated circuits, and satellite antennas.
He has published over 700 journal paps and more than 35 books or book chapters on various topics related to electromagnetics, antennas, microwaves and electronic packaging. He also has three patents on communication antennas to his credit. He has supervised 84 Ph.D. theses, 85 M.S. theses, and has mentored more than 50 postdocs and Visiting scholars. For the last 15 years he has directed, as well as lectured in, numerous short courses on Computational Electromagnetics, Electronic Packaging, Wireless antennas, both nationally and internationally.
Tuesday, 15th February, 2005,1500 hrs
"SoC Applications: HW/SW Co-Design of MPEG-4 Video Decoder on Excalibur chip and FPGA Implementation of RTE-LDPC Encoder/Decoder "
by Prof. Yong Cho ,Konkuk University ,Korea
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay and IEEE AP/ED Bombay Chapter
Abstract: HW/SW Co-Design of MPEG-4 Video Decoder on Excalibur chip
MPEG-4 Video Decoder was implemented using Altera Excalibur chip that has 400,000 PLD gates and an ARM 922T core. Among MPEG-4 Video Decoder blocks, IDCT and M.C. (Motion Compensation) blocks have more calculation complexity than other blocks. IDCT and M.C. blocks was implemented hardware IP on PLD area and the other blocks will be implemented by software on ARM922 core in order to reduce total operation cycles.
FPGA Implementation of RTE-LDPC Encoder/Decoder Decoder procedure of LDPC (Lower Density Parity Check) is based on IBPA (Iterative Belief Propagation Algorithm) compared with turbo codes' BCJR Algorithm. LDPC is not only reduced a delay time and a computational complexity but got a global convergence. However, this procedure has an inordinate demand of calculation operations. To do overcome this demand, RTE (Real Time Encodable)-LDPCs design is required. The FPGA implementation will be based on an algorithm based on Ping and Echard's paper. The performance of FPGA will be verification using Excalibur chip.
About the Speaker Yong Cho is currently working as a Professor in the Department of Electronics Engineering at Konkuk University in Seoul, Korea. He received the Ph.D. degree in Electrical Engineering from Case Western Reserve University, Ohio, 1992. He was a Visiting Professor in SoC lab at the University of British Columbia, form 2001 to 2002. His research interests include SoC design, hardware/software codesign for real time applications, and Applications for Embedded System.
Mon - Wed 7 - 9th Feb,2005
3rd Intl Confce "Communications Convergence: The Change Agent"
Venue: Hilton Towers, Mumbai
Jointly with IMC, Mumbai
http://imcnet.org
Monday, 7th February, 2005,1430 hrs
"TRANSITIONING FROM A "LINEAR" WORLD TO A "COMPUTATIONALLY INTELLIGENT NONLINEAR" WORLD "
by Prof. Rui J. P. de Figueiredo, FIEEE, Past President and Past DL of the IEEE CAS Society
Laboratory for Intelligent Signal Processing and Communications
The Henry Samueli School of Engineering, University of California, Irvine Irvine, CA 92697-2625, USA
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay
Abstract: Linear models have provided the foundation for the theory and techniques supporting most of the technological developments of the past century. However, natural and artificial systems which possess some form of computational intelligence, like the human brain, are, in general, large-scale, parallel, distributed, and nonlinear (ls/p/d/nl). With the explosive growth and enormous potential of information technologies (IT) in this new century, it is of paramount interest to develop a rigorous framework for modeling identification and design ls/p/d/nl systems capable of performing computationally intelligent tasks. Motivated by these considerations, we will present in this lecture a space F(X) where the input/output maps f of ls/p/d/nl systems may reside. In mathematical terms, F(X) is a Reproducing Kernel Hilbert Space of nonlinear (not-necessarily linear) analytic functionals (abstract Volterra series) on a given input vector space X. In general, f will consist of a m-tuple of maps in F(X). We will show how a solution to the problem of optimal identification or design of f is obtained by an orthogonal projection in F subject to input-output data constraints or design specification constraints. Such a solution naturally appears in the form a feed-forward or recurrent neural system. We will briefly discuss the processes of adaptation, learning, evolution, discovery, and invention by such systems. Examples with simulated and real data will be presented.
About the Speaker Prof. Rui J. P. de Figueiredo, B.S. and M.S. (MIT), Ph.D. (Harvard), served on the faculty of Rice University, Houston, Texas until 1990, where he was the Founding Chair of a Consortium of four Texas universities (Rice, UT-Austin, UT-Arlington, and Texas A&M) for support of the Space Station Automation at the Johnson Space Center. In 1990 he joined the faculty of UC-Irvine where he is Professor of Electrical Engineering and Computer Science, Biomedical Engineering, and Mathematics, and Director of the Laboratory for Intelligent Signal Processing and Communications. He has served in various leadership positions in his field, including that of President of the IEEE Circuits and Systems Society in 1998. For his accomplishments he has received a number of awards including the IEEE Fellow Award, the IEEE Distinguished Lecturer Award, the IEEE Tri-Millennium Medal, the IEEE Circuits and Systems Society 1999 Golden Jubilee Medal, 1994 Technical Achievement Award, 2002 M. E. Van Valkenburg Society Award, and 2003 Guillemin-Cauer Best Paper Award, the 2000 IEEE Neural Networks Society Best Paper Award, the 2003 Gh. Asachi Medal from Romania's Technical University of Iasi, the 2004 Honorary Membership of the Russian Popov Society, and the election into the UN-Affiliated International Informatization Academy.
9th to 11th January 2005
Visit of IEEE President Dr W. Cleon Anderson, P.E.

7 - 8th January 2005
"International Conference On Multidisciplinary Aspects Of Engineering - IMAE05 Focal theme - Role of electronics Engineering"

Wednesday, 5th January, 2005,1530 hrs
"Lecture on "Satellite Communications Status & Trends"
by Dr. Sajjad Durrani, Distinguished Lecturer and FIEEE
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with IIT Bombay
Abstract: The satellite communications technology has made tremendous advances since its inception in the mid-1960s, and the industry continues to flourish in spite of occasional setbacks. The talk will give an overview, followed by a brief discussion of the basic concepts and techniques involved; typical satellites and earth stations; and the major services currently available. It will also touch upon domestic and international regulatory issues, and discuss the trends.
Biographical Sketch: Sajjad Durrani was born in 1928. He received his undergraduate education in Pakistan, a Master's degree from England in 1953, and a doctorate from the University of New Mexico in 1962, all in Electrical Engineering. He taught for more than 10 years in several universities, and had industrial experience of another 10 years with GE, RCA, Comsat Labs, etc. He then joined NASA in 1974 and held research and management positions in the area of space communications at Goddard Space Flight Center and at NASA Headquarters. After retiring from NASA in 1992, he worked with Computer Sciences Corporation till 1998. He was a Guest Lecturer on space communications at the International Space University in Strasbourg, France in 1998, and a Consultant to SUPARCO in Lahore under the UN Development Program in 1999. In 2000-2001 he was an IEEE-USA Executive Fellow with the Federal Communications Commission in Washington, DC. He is now serving under a similar program with the U.S. Department of State, as a Technical Advisor to its International Communications and Information Policy Office. Dr. Durrani is a Fellow of the IEEE and has been active in the IEEE for more than 35 years. He was Chair of the Washington Section in 1980-81, President of the Aerospace and Electronic Systems Society in 1982 and 1983, and a member of the IEEE Board of Directors in 1984 and 1985. He has served on four major IEEE Boards and on the Editorial Boards of the IEEE SPECTRUM and PROCEEDINGS of the IEEE. More recently, he was Chair of the IEEE National Capital Area Council in Washington, D.C. in 2002. He has also served as an ABET Program Evaluator for Electrical Engineering at several universities. Dr. Durrani has given courses on Satellite Communications in the U.S. and more than 25 other countries. He has received several awards from the IEEE, NASA, and CSC. He is an Associate Fellow of the American Institute of Aeronautics and Astronautics (AIAA), and a Fellow of the Washington Academy of Sciences, where he was one of its Vice Presidents from 2001 to 2004.
"Annual General Body Meeting"... Notice...Saturday 11th December 2004
- Slate given by Nominations Committee
- RSVP Letter of Acknowledgement
- Newsletter
- Events in 2004
Wednesday, 8th December, 2004 ,1100 hrs
Lecture on " Recent advances in Wireless and Mobile Systems "
by Dr Dharma Agrawal, FIEEE, University of Cincinnati, USA http://www.ececs.uc.edu/~dpa
Venue: Seminar Hall, KReSIT, IIT Bombay, Powai, Mumbai.
This lecture will be broadcast live to 11 remote centres attached to IIT Mumbai with facility for participants in the remote centres to interact with speaker
Jointly with COMSOC Bombay Chapter

Friday, 19th November, 2004 ,1800 hrs
Lecture on " Power Quality "
by Dr. Rao S. Thallam , Senior Principal Engineer , Electric System Planning & Engg. Dept. , Salt River Project , Arizona , U.S.A.
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with PES / IAS Society Bombay Chapter and IIT Bombay

Monday, 1st November, 2004 ,1530 hrs
"Lecture on Towards Automatically Switched Optical Networks (ASON)"
by Prof. Andrzej JAJSZCZYK, FIEEE , AGH University of Science & Technology, Krakow, Poland
Venue: EE Seminar Hall , I.I.T. , Powai , Mumbai
Jointly with Comm Society Bombay Chapter and IIT Bombay

Abstract: Growing competition between network operators, new characteristics of traffic as well as network survivability challenges trigger the need to migrate from SDH/SONET-based networks to a more flexible and dynamic optical infrastructure. The proposed lecture will present current standards and concepts related to such an infrastructure and ways to implement it in real networks, along with challenges facing designers and system engineers. The lecture presents migration from current networks towards Automatic Switched Optical Networks (ASON) that give the means to deliver end-to-end, managed bandwidth services efficiently, expediently and at reduced cost. Current status of optical networking is outlined and driving forces behind ASON are enumerated. Transport, control, and management planes of ASON are described, including such issues as: optical cross-connects, control plane models, and management of optical networks. Approaches to service resilience in optical networks using the ASON functionality are reviewed. The lecture is concluded by presenting current standardization activities, open issues and perspectives of ASON. Biography : Andrzej Jajszczyk is a Professor at AGH University of Science and Technology in Krakow, Poland. He received M.S., Ph.D., and Dr Hab. degrees from Poznan University of Technology in 1974, 1979 and 1986, respectively. He spent a year at the University of Adelaide in Australia and two years at Queen's University in Kingston, Ontario, Canada as a visiting scientist. He is the author or co-author of six books and more than 180 scientific papers, as well as 19 patents in the areas of telecommunications switching, high-speed networking, and network management. His current research interests focus on control plane architectures for transport networks, quality of service and network reliability. He has been a consultant to industry, telecommunications operators, and government agencies in Poland, Australia, Canada, France, Germany, and the USA. He was the founding editor of the IEEE Global Communications Newsletter, editor of IEEE Transactions on Communications, and editor-in-chief of IEEE Communications Magazine. Since January 2004 he is Director of Magazines of IEEE Communications Society. He has been involved in organization of numerous technical and scientific conferences. He is an IEEE Communications Society Distinguished Lecturer. He is a member of the Association of Polish Electrical Engineers and a Fellow Member of IEEE. Andrzej Jajszczyk is Vice-President of the Kyoto-Krakow Foundation, fostering cultural and technical relations between Asia and Poland.

Wednesday 19th May 2004 , 2 - 6 pm

Half-day Workshop on "The Art of Analog Design"

Monday 17th May 2004, 1645 - 1815 hrs
"36th World Telecom Day Celebration"
by Dr. D.B. Phatak , Subrao Nilekani Chair Professor IIT Mumbai
will deliver the keynote address on this year’s ITU theme
" ICTs: Leading the Way to Sustainable Development"
Venue: Conference hall Western Railway HQ office 2nd Floor old Building, Churchgate, Mumbai
Jointly with IETE , IRSTE, IEE, BESI

Saturday 20th March 2004 , "Year 2004 Prof K Shankar Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
National Seminar " Electrifying India - Engineering Management in Power Sector, 12-13 Feb 2004, Hyatt Regency Mumbai - IEEE EMS Chapter

Fri 6th Feb 2004 , 1700 hrs
"Cyber Crimes"
Shri I M Zahid, Senior Inspector of Police, Gamdevi Police Station, Mumbai
Venue: Conference Hall, 2nd Floor, Old Building, Western Railway Headquarter Office, Churchgate, Mumbai - 400 020
Jointly with IETE, IRSTE, IEE

Fri - Sun, 16 - 19th January, 2004
Short term Course on "ADSP applications with hands on experience"
Course Coordinator Dr. (Mrs.) M.A.Joshi
Venue: Dept. of E & TC , Pune Institute Of Engineerin &Technology, Pune - 05
Jointly with IEEE WIE Affinity Group, IEEE Pune Subsection, Dept of E&TC PIET, Pune
Course Brochure

Monday, 12th January, 2004 ,1500 hrs
"Lecture on Sigma-Delta Converters"
by Prof. Paul Jespers , FIEEE , IEEE Distinguished Lecturer , Catholic University , Belgium
"Techniques for very low-voltage operation of continuous-time analog CMOS circuits"
by Prof. Jaime Ramirez-Angulo, IEEE Distinguished Lecturer , Director of the VLSI lab , Klipsch School of Electrical and Computer Engineering, New Mexico State University in Las Cruces, New Mexico (USA)
Venue: EE Seminar Hall , IIT Bombay , Powai, Mumbai
Jointly with IEEE CAS India Chapter, and IIT Bombay

Tuesday, 6th January, 2004 ,1600 hrs
"Lecture on Submicron Silicon Technologies"
by Prof. Cor Claeys IMEC, Kapeldreef 75, B-3001 Leuven, Belgium. Also at E.E. Dept., KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
Venue: Thadomal Shahani Engineering College, Bandra (W), Mumbai
Jointly with IEEE AP/ED Bombay Chapter, and IEEE Student Branch of Thadomal Shahani Engineering College:
Abstract: The International Technology Roadmap for Semiconductors (ITRS) is predicting the technology evolution for the coming 15 years, required to give the semiconductor industry a competitive market position. This not only implies pushing existing process modules to the limits but also introducing new ones, which most likely will be based on alternative concepts and/or the use of new materials. This presentation will be focusing on a selection of these processing challenges. First the silicon material requirements will be addressed, including high quality silicon substrates, epitaxial wafers, thin film SOI, SiGe and strained silicon. Subsequently some process modules will be discusses such as e.g. as isolation schemes, gate dielectrics based on high-k materials, silicides and interconnect schemes. Beside the use of novel or alternative materials, attention will also be given to equipment aspects like atomic layer deposition, single wafer processing, flash annealing, etc The last part will outline the importance of so-called gate engineering, including metal gates, doubles gate structures, vertical replacement gates and FinFETS. These approaches are presently extensive studied and will surely be used for the 45 nm and below emerging silicon technologies.
Short Biography of the speaker: : Cor Claeys was born in Antwerp, Belgium. He obtained his Electrical Engineering Degree and his Ph.D. at the Catholic University of Leuven, Belgium, respectively in 1974 and 1979. He was staff member of the ESAT laboratory before joining IMEC in 1984 as Head of Silicon Processing. Since 1990 he is heading a research group on Radiation Effects, Cryogenic Electronics and Noise Studies. He is also responsible for Technology Business Development and Professor in Material Science at the Catholic University of Leuven. He is author and co-author of more than 500 international publications, eight book chapters, co-edited a book on "Low Temperature Electronics", wrote a book on "Radiation Effects in Advanced Semiconductor Materials and Devices" and co-authored more than 450 contributions at International Conferences (of which 25 invited presentations since 1990). Editor or co-editor of 20 Conference Proceedings Volumes. He is member of several societies and committees, of which the most important are: Chairman of the Executive Committee of the Electronics Division of the Electrochemical Society, Elected member of the EDS AdCom, and Chair of the EDS Regions/Chapters. He is a fellow of the Electrochemical Society, a Senior member of IEEE, and was in 1999 elected as Academician and Professor of the International Information Academy. His main interests are in silicon processing, device physics, low temperature electronics, radiation physics, submicron silicon technologies, defect engineering, and low frequency noise.
January 5 - 9 , 2004
"VLSI Design 2004"
The Seventeenth International Conference on VLSI Design
and
The Third International Conference on Embedded Systems Design
Venue: Renaissance Mumbai Hotel and Convention Centre Mumbai, India
For more details visit vlsi2004.pdf

Tuesday, 16th December, 2003 ,1500 hrs
"Lecture on Ultra Thin Plasma Nitrided Gate Dielectric for 65nm CMOS Platform"
by Dr. Lucky Vishnubhotla Motorola-Philips Semiconductors-STMicroelectronics Alliance 850 rue Jean Monnet, 38926 Crolles, France
Venue: Seminar Room , Electrical Engg. Dept.,I.I.T. , Powai , Mumbai
Jointly with IEEE AP/ED Bombay Chapter, IEEE CPMT India Chapter and IIT Bombay
Abstract: Incorporation of nitrogen into the gate dielectric has been well known to reduce gate leakage for CMOS devices. However, for 65nm technology, the scaling down in conventional methods of nitridation (Rapid Thermal Nitridation and Furnace Oxynitride) processes of gate dielectric has not proven to be useful due to intolerable gate leakage currents coupled with poor device performance. In addition, conventional nitrided gate dielectrics have also been found to be a major concern for reliability. Recent developments in plasma nitridation processes have been proven to be successful not only in meeting the CMOS platform requirements but also in supporting the 300mm activities. Single wafer plasma nitridation tools in the 300mm facility have been found to introduce substantial amounts of nitrogen into the gate dielectric, thus leading to reduced gate leakage currents, without causing degradation in the device performance. XPS and D2R (Delay to Re-oxidation) techniques have been developed to monitor the nitrogen dose and profile routinely in the thin gate dielectric. This talk focuses on the recent developments in gate dielectrics at Crolles, France (Motorola, STMicroelectronics, and Philips alliance team) for 65nm technology and possibly even for future generations.
"Annual General Body Meeting"... Notice...Saturday 13th December 2003
- Slate given by Nominations Committee
- RSVP Letter of Acknowledgement
- Newsletter
Friday 12th Dec 2003 to Sunday 14th Dec 2003
ACE 2003
Theme... "Emerging Technology Trends"
Saturday, 4th October, 2003 , 1400 - 1730 hrs
"EDS Mini Colloquium"
Venue: Seminar Hall , Electrical Engg. Dept.,I.I.T. , Powai , Mumbai
Jointly with AP/EDS Bombay Chapter
- 2 - 3 pm "RF MEMS Design", Dr. Navakant Bhat, Indian Institute of Science, Bangalore
- 3 - 3:45 pm "Microstructural Damages Induced by Gate Dielectric Stressing in Sub-micron Devices", Dr. M.K. Radhakrishnan, National University of Singapore
- 3:45 - 4:15 pm Tea break/Snacks
- 4:15 - 5:15 pm "Nano-FET Fluctuation Physics", Dr. Renuka P. Jindal, University of Louisiana at Lafayette
For more information, please contact Prof. V.Ramgopal Rao at rrao@ee.iitb.ac.in

Friday, 3rd October, 2003 ,1500 hrs
"Lecture on Advanced Control Techniques in Modern Electrical Drives "
by Prof. Alfio Consoli , Distinguished Lecturer - IEEE , Prof. at University of Catania , Italy since 1965 . Topics of interest : Energy conversion , Electrical drives , Robotics and Power Electronics
Venue: Seminar Room , Electrical Engg. Dept.,I.I.T. , Powai , Mumbai
Jointly with IAS/PES Bombay Chapter
About the Speaker: Dr Alfio Consoli (F’00) was born in Catania, Italy, in 1949. He graduated in Electrical Engineering from the Politecnico di Torino, Torino, Italy.
During 1973-1974 he was with FIAT, Torino, Italy. In 1975, he joined the Department of Electrical, Electronic, and Systems Engineering, University of Catania Italy, where, he has been a professor of electrical engineering, teaching since 1985, in the areas of electrical machines and power electronics. His research activities include energy conversion systems, electrical drives, robotics, and power electronics, having been involved in the frame of industry cooperation, as well as national and international research programs. In 1980, he spent a year as the recipient of a NATO Grant at the Purdue University, West Lafayette, IN, and in 1985 he was a visiting professor at the University of Wisconsin, Madison, USA, teaching classes in electromagnetic design. Since 1987, he has been the coordinator of the scientific activities of Ph.D. candidates in Electrical Engineering at the University of Catania. He is a member of the scientific committee of CORIMME, the consortium for research on Microelectronics between the University of Catania and the ST-Microelectronics. During 1993-99 he has been the delegate of the Catania University Rector for research matters and a member of the European Research Policy Working Group of the confederation of European Union Rectors Conference.
Dr. Consoli is the author of more than 150 technical papers and holds two patents. He is also the co-author and the co-editor of the book “Modern Electric Drives” (Amsterdam, the Netherlands: Kluwer, 2000). He won the Third Prize Paper Award of the Industrial Drives Committee of the IEEE Industrial Application Society in 1998 and the Best Transactions Paper of the IEEE Power Electronics Society in 2000. Professor Consoli is a member of the Italian Electric Association (AEI), of the European Power Electronics Association (EPE) where he serves as a member of the International Steering Committee, and a member of several technical committees of IEEE Societies.
During 1996-2000 he was a member of the Executive Board of the IEEE Industry Applications Society. Starting 2002 he is the chairman of the Technical Committee on Motor Drives of the IEEE Power Electronics Society.
Friday, 26th September, 2003 ,1520 hrs
"Tutorial on Current Issues & problems in Distributed Generation"
by Dr. Koepfinger - BSE (EE), 1949, MSE - 1953, Chairman (Past & Present) on various committees of IEEE.
Venue: Conference hall, MSEB, Prakashgad, Bandra(E)
Jointly with IAS/PES Bombay Chapter
Abstract: He has witnessed distributed generation (small city systems & captive generations) evolving into huge regional power grids though his career spanning over 53 years by now. The scenario is changing again. Standards have been evolved on interconnections, surge problems, etc.
Deregulation of the power industry is changing the playing field and providing customers new opportunities to have more input into the type and quality of their electric service. This is providing an opportunity for the re-birth of distributed energy resources (DER) or distributed resources (DR). The development of the modern DR and its utilization is taking many forms. Some are being operated to back up existing electrical facilities, others are the prime source of electricity, operating individually or in a microgrid and others are being operated as an integral part of the existing electric supply system.
This tutorial will review the evolution of DR, the types of DR and their characteristics, the problems and requirements associated with operations in a microgrid and in the integration with an existing electrical system. Consideration will be given to operation limitations, protection, control, communications and safety issues. There will be a discussion of some typical installations such as combined cycle installation and efficiencies.
Some material will address the problems associated with the interconnection of DR on electrical power distribution systems. Key to the success of the discussions will be the understanding of the terminology by all of the participants, including the instructor.
The tutorial will focus on the recent development of IEEE 1547.1 Interconnection of DR and other standards under development in the 1547 series of standards. This will be an interactive tutorial where the participants will have an opportunity to raise issues and have them discussed by the participants.
About the Speaker: Honors : Numerous IEEE & National awards for excellence.
Member of the Hall of Honor of the Electric League of Western Pennsylvania.
Specialization -
1) Transient & Surge protection.
2) Power system relays & protection systems.
3) Development of standards
4) Cable failure, Manhole explosions, transformer fire control.
5) Interconnection between distributed generation like cogeneration & major power grids.
Monday, 4th August, 2003 ,1530 hrs
"Intel Distinguished Lecture Series"
"Network Processors: Building blocks for robust and programmable networks"
by Dr. Raj Yavatkar , Chief Software Architect , Intel Corporation, USA
Venue: F C Kohli Auditorium, Kanwal Rekhi School of IT (KReSIT) IIT Bombay, Powai, Mumbai 400076
Jointly with Intel(R) Innovation In Education & IIT Bombay
Abstract: Both service providers and enterprise IT are facing the problem of rising OpEx (Operational Expenses) and complexity of managing the infrastructure. In addition, service providers lack visibility into network traffic to offer value-added services such as prevention of DOS (Denial of Service) attacks, virtual network services and SLAs based on differentiated services. This talk, will describe the problem of creating robust IP-based network infrastructure that supports value-added services. We will then argue that programmable network processors provide a suitable platform to achieve such an infrastructure
About the Speaker: Raj Yavatkar is currently the Chief Software Architect at the Intel's Network Processing Group. His main areas of interest include programmable networks, programming languages and tools for network processors, and self-managing systems. He has been one of the main architects of the software infrastructure for Intel's IXP series of network processors. Previously, he led the advanced R&D activities in the areas of programmable networks, policy-based network management, and end2end Quality of Service (QoS). He initiated and led the definition of a new industry-wide framework for policy-based networking that resulted in both the development of IETF standards (e.g., COPS) and the technology that Intel licensed to HP OpenView and others. Raj Yavatkar received his Ph.D. in Computer Science from Purdue University in 1989. He has numerous publications to his credit and serves on the technical program committees of leading conferences and workshops. He also co-authored the book "Inside the Internet's Resource reservation Protocol (RSVP)" published by John Wiley in 1998. He currently serves on the editorial board of the IEEE Network magazine and previously served as the US Editor of the journal Computer Communications and as a member of the editorial board of ACM/Springer-Verlag Multimedia systems and Kluwer's Multimedia Tools and Applications..
Interested members and students can register their confirmation at
www.ar.educationinindia.net/tlaug0403.htm
Friday, 25th July, 2003 ,1600 hrs
"Performance Metrics and Issues For Interconnections In VLSI "
by Kartik Raol, Intel Corp., USA
Venue: EE Seminar Hall , IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter
Abstract: Stochastic wiring distribution models based upon Rent's rule have been in use for the design of multilevel interconnect systems for microprocessors. A methodology and a performance metric to design a multilevel interconnect architecture that was developed earlier is presented. One of its features is the ability to predict the wiring requirements, the area (die size) of the microprocessor chip or macrocell, and the length distribution of the wires. As microprocessor clock frequencies increase well into the gigahertz domain, increasing attention is being paid to the role of interconnects as both performance limiters and their role in design and manufacturing complexity. In this regard system level interconnect prediction is likely to play an important role in managing these complexities, and an overview of metrics, models and issues relevant to the design of the interconnect process architecture is provided.
About the Speaker: Kartik Raol obtained has BSEE from the Univ. of Texas at Austin and MSEE from the Univ. of Cincinnati. He is currently a Staff Engineer with Portland Technology Development, Intel Corporation, Hillsboro, Oregon. His interests are in the areas of interconnect and device modeling. Prior to joining Intel he was with Digital Equipment Corporation, Hudson, MA (1987-1995) where he worked on interconnect models for extraction tools, statistical circuit design, and non-quasi static effects in MOS devices.
Saturday, 17th May, 2003 ,1600 hrs
35th World Telecom Day
"Romance with Rural Telecommunication "
by Dr B D Pradhan
Venue: AIR Auditorium, Behind Mantralaya
Jointly with IETE,IRSTE, BES, IEE
Report on the lecture
Monday, 12th May, 2003 ,1430 hrs
"Polysilicon Piezoresistive Pressure Sensors"
by Prof. K. N. Bhat , IIT Madras
Venue: EE Seminar Hall, IIT Bombay
Jointly with IEEE AP/ED Chapter and IIT Bombay
"Results of Year 2003 IEEE Bombay Section Student Paper and Project Contest"
Saturday 5th April 2003 , "Year 2003 IEEE Bombay Section Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
Thursday, 20th March, 2003 ,1500 hrs
"Nanocrystalline Si:H : A New Material for Electronic and Optical Devices"
by Prof. Vikram L. Dalal , Whitney Professor of Electrical and Computer Engr ,Iowa State University, Ames, Iowa, USA, NJ
Venue: EE Seminar Hall , IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter and EE Dept IIT Bombay
Abstract: Nanocrystalline Si:H (sometimes also called microcrystalliine Si:H) is a new electronic material where the grain size is extremely small, of the order of 10-30 nm. It is deposited at low temperatures (< 350 C) using plasma deposition from a mixture of hydrogen and silane, though under some circumstances, one can deposit it without using any additional hydrogen. The grain size can be controlled by controlling temperatures, hydrogen dilution ratio and ion bombardment during growth. The presence of hydrogen in the material is critical. H both passivates the grain boundaries, and makes possible the crystallization process because of its etching effect during growth. In spite of the small grain size, the material has very good electronic properties, with Hall mobilities in the range of 10 cm2/V-sec, and hole diffusion lengths of up to 10 micrometers. The material can be doped both n and p type, thereby making devices possible. The optical properties resemble those of crystalline Si, but with an enhanced absorption due to internal scattering at grain boundaries. In this talk, I will discuss the nature of the material, and its structural, optical and electronic properties. I will also discuss device applications and device designs, including thin film transistors and solar cells. This material may offer the potential of building good devices on plastic substrates, including "wearable" electronic devices, as well as the potential of making thin film, low cost, crystalline Si solar cells of > 15 % efficiency.
About the Speaker: Prof. Vikram J. Dalal obtained his BE from Bombay University and his Ph.D. from Princeton University. He worked for several companies including RCA Labs, Polaroid Corp and Chronar Corp, before joining Iowa State University. He is currently the Whitney Professor of Electrical and Computer Engineering there. His research interests have included organic semiconductors, photovoltaic devices, nanocrystalline and amorphous semiconducting materials, and thin film transistors.
Friday, 24th January , 2003 ,1500 hrs
"Minimum Dynamic Power CMOS Circuits"
by Dr. Vishwani D. Agrawal, FIEEE ,Visiting Professor, ECE Dept , Rutgers University , New Brunswick, NJ
Venue: EE Seminar Hall , IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter and EE Dept IIT Bombay
Abstract: The dynamic power consumption of a CMOS circuit is at least an order of magnitude greater than the other components such as the short-circuit and steady-state power. We prove that the minimum dynamic power design, which is completely free from glitches, is obtained when the differential path delay at every gate is less than the inertial delay of the gate. When the overall input to output delay is also constrained, we obtain the minimum power design by a linear program (LP) consisting of an inequality set whose size is linear in the circuit size. The LP determines the delays for all gates. For physical implementation, we express the delays of CMOS gates as linear functions of the length/width ratios of transistors. Routing delays are entered in the LP as constants and their values are determined through iterations of the LP and physical layout. The optimized design of the benchmark c7552 consumes 38% average power as compared to the original unoptimized circuit.
About the Speaker: Vishwani D. Agrawal has over thirty years of industry and university experience, working at Bell Labs, Murray Hill, NJ; Rutgers University, New Brunswick, NJ; TRW, Redondo Beach, CA; IIT, Delhi, India; EG&G, Albuquerque, NM; and ATI, Champaign, IL. His areas of expertise include VLSI testing, low-power design, and microwave antennas. He recently retired from Agere Systems to pursue a full-time academic and consulting career. Currently, he is an Visiting Professor of ECE at Rutgers University, New Brunswick, NJ, a position he has held since 1990. He holds a BE from University of Roorkee, ME from the Indian Institute of Science, and PhD from the University of Illinois at Urbana- Champaign. He has published over 250 papers, has coauthored five books and holds thirteen United States patents. He is the Editor-in-Chief of the Journal of Electronic Testing: Theory and Applications (JETTA) and the Consulting Editor of the Frontiers in Electronic Testing Book Series. He co-founded the VLSI Design Conference and the VDAT Workshops. He is the recipient of seven Best Paper Awards, the Harry H. Goode Memorial Award, and the Distinguished Alumnus Award of the University of Illinois. He is a Fellow of the IETE (India), a Fellow of the IEEE, and a Fellow of the ACM. See his website, .
Friday, 10th January 2003 ,1430 hrs
"Electro Static Discharge (ESD): From Black Magic to CAD Assisted Methodology"
by Dr. Natarajan Iyer , IMEC , Belgium
Venue: EE Seminar Hall , IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter and EE Dept IIT Bombay

Thursday, 9th January , 2003 ,1430 hrs
"The Evolving Structure of the Semiconductor Industry"
by Dr. Pushkar Apte , McKinsey and Co., USA
Venue: EE Seminar Hall , IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter and EE Dept IIT Bombay
Abstract: Over the past few years, the semiconductor industry has morphed through a transformation driven by technology and economics. The impact has been that an industry formerly dominated by large vertically-integrated players following a "do-it-all-yourself" business model has given way to an "atomized" ecosystem, with a large number of players of varying sizes and following varying business models. There are two primary drivers of this transformation - one, the sheer cost of developing process technology at advanced nodes (e.g., <= 130 nm) and two, the increasing complexity of design. This has caused separation of process and design, and has fueled the rise of the foundry business model, where the foundries have emerged as the aggregators of manufacturing capacity. In conjunction, many players have emerged that follow capital-light, "fabless" business models, which include providing designs, intellectual property, cell libraries, embedded software, consulting and project management services. The new industry structure will inevitably be more complex, and the complexity is further intensified by the geographic dispersion of activities. In particular, the greater China region has emerged as a strong player in manufacturing, and is increasingly seeking a leading role in Design/Product R&D as well as Process R&D. These changes are altering not just the business systems, but are fundamentally altering both the nature and ownership of R&D activities. In this talk we will explore this industry transformation, and the implications for industry and academia.
About the Speaker: Dr. Pushkar P. Apte did his Ph.D. from Stanford University in the area of VLSI technology. He subsequently worked with TI, USA for several years. Since 1999, he has been with McKinsey, based in the Bay area, as their area expert for the semiconductor industry.
Friday, 20th December , 2002 1130 hrs
"Embedded DRAM Technology and the System-on-a-Chip"
by Subramanian S. Iyer, FIEEE , Semiconductor Research and Development Center , IBM Microelectronics Division , Hopewell Junction NY 12533, USA
Venue: Conference Room, Electrical Engineering Department, IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter , CPMT India Chapter and EE Dept IIT Bombay
Abstract: Technological innovation in the areas of lithography, novel materials, and device design has made relentless strides in the microelectronics area over the last few decades. We will begin by highlighting recent developments in these areas at IBM. However, further returns in functionality and performance will come through the use of system level integration on chip ? often referred to as the System on a Chip (SOC). A key component of the an SOC is the memory subsystem which has traditionally been the purview of SRAM. However, the need for increased density, and the fact that further scaling of device technology results in a concomitant increase of standby power, as well as an increase in soft error rates (SER) are severe limitations. We have successfully embedded DRAM in to advanced logic technologies without compromising logic performance. We describe our deep trench-based technology and embedded DRAM macro concepts, which we are extending well into the 65nm node for both bulk and SOI technologies. This technology is now a critical component of modern network switches and high-end server caches including the IBM Blue Gene supercomputer. Another aspect of the SOC era is the integration of test and repair function on chip. We will describe our built-in test and repair methodology using a novel type of electrical fuse element and discuss the concept of autonomic chips that have the potential for self-diagnosis and self-repair.
About the Speaker: SUBRAMANIAN S. IYER obtained his B.Tech in Electrical Engineering at the Indian Institute of Technology, Bombay in 1977, and his M.S. and Ph.D. in Electrical Engineering at the University of California at Los Angeles in 1978 and 1981 respectively. He joined the IBM T. J. Watson Research Center in 1981 and was manager of the Exploratory Structures and Devices Group till 1994, when he founded SiBond LLC to develop and manufacture Silicon-on-insulator materials. Since 1997 he has been with the IBM Microelectronics Division, Semiconductor Research and Development Center, where currently, he manages the embedded DRAM project. Dr. Iyer has received two outstanding Technical achievement awards at IBM for the development of the Titanium Salicide process and the fabrication of the first SiGe Heterojunction Bipolar Transistor. He has received 15 Invention plateau awards and has authored over 150 articles in technical journals and several book chapters. Dr. Iyer is an Adjunct Professor of Electrical Engineering at Columbia University, New York, and a fellow of IEEE.
Thursday, 18th December , 2002 1600 hrs
"Power Electronics --- Past, Present and Future"
by Ajit K Chattopadhyay, Fellow IEEE , Distinguished Lecturer of the IEEE Industry Applications Society
Venue: Conference Room, Electrical Engineering Department, IIT Bombay, 400 076
Jointly with AP/ED Bombay Chapter and EE Dept IIT Bombay
Abstract: Power electronics (PE) has a long history and evolving development since the beginning of electro-physics in the eighteenth century with the concept of the `semiconductor'. Its technology has gone through an unanticipated rapid growth in the last forty years. The presentation begins with a plausible definition and the goal of power electronics with its key features and application areas for a better understanding, and traces ,chronologically, the major significant events / breakthroughs in the past history ( since 1783 ) till the birth of the Silicon Controlled Rectifiers in 1957 , that shaped the growth of PE as it today. Then, the evolution of modern power electronics as a complex multidisciplinary technology synthesizing a number of diverse disciplines such as power switching devices, new materials, microelectronics , converter topologies, controls, integration and packaging technologies, and its continuing applications to all cases of power processing: generation, transmission, distribution and utilization (including machine drives) have been dealt with, again in a chronological order, till the present date. The objective is to make an attempt for a comprehensive review of the past and the present status of the developments in PE in almost all possible areas and to assess the future trends of this dynamic technology in the next few years of the 21st Century. It is demonstrated that in the highly automated and economically competitive environment worldwide in this century, the PE will truly be a key enabling technology in every field.
"Annual General Body Meeting"... Notice...Saturday 14th December 2002
- Slate given by Nominations Committee
- RSVP Letter of Acknowledgement
- Newsletter
- Secretary Report for the year 2002
- Events in 2002
Thursday, 12th December, 2002 1500 hrs
"Energy Management- Electrical Power"
by Dr. M. Safiuddin, Fellow IEEE , President, STS International, USA
Venue: Conference Room, Electrical Engineering Department, IIT Bombay, 400 076
Jointly with PES/IAS Bombay Chapter
Abstract: Electricity, power tools, and automation in factories, began the Industrial Age at the end of the Depression in the last century. After the Second World War, we entered the Atomic Age which gave us the technology to build nuclear power plants for production of, the so-called, cheap electricity during the decades of the fifties and the sixties. Challenge to land the man on the moon and bring him back safely started the decades of the Space Age. Advancements in microelectronics, computers, and the Internet brought in the Information Age, bringing with it productivity gains in the white-collar workers of the industry and the dotcom revolution, during the last decade of the past century. Rapid expansion of economies throughout the world, and simultaneous increase in standards of living, for an exponentially growing population, have started to increase pressures on energy demand for both fossil fuels and electricity as we embark upon this new century and the third millennium. We, therefore, have now entered the Energy Age. This seminar will cover topics related to the management of electrical power. After a brief background on energy consumption trends and power quality and reliability concerns, both supply side and demand side issues would be presented.
About the SpeakerDr Mohammed Safiuddin received the B.E. (Electrical) degree from Osmania University, Hyderabad, India in 1959 and the MSEE degree from the University of Illinois in 1960. Later he received the MBA and Ph.D. degrees from the State University of New York at Buffalo in 1971 and 1982 respectively.
Having worked as Junior Engineer in Andhra Pradesh State Electricity Board (India) for over a year before arriving in the USA, he joined the Systems Control Department of Westinghouse Electric Corporation, Buffalo, New York in June of 1960 as an Associate Engineer. He progressed through the ranks of Engineer, Senior Engineer and Fellow Engineer positions to become Manager, Product/Strategic Planning in 1982 in the Power Electronics and Drive Systems Division and was later appointed Technical Advisor in the Marketing Department of the same Division. His interests in continuing education has kept him in close contact with the State University of New York at Buffalo (SUNYAB) where he has done part-time teaching since early sixties and has served as Adjunct Associate Professor (1977-91). He is currently Research Professor (part-time), Advanced Technology Applications, in the Electrical Engineering Department at SUNYAB. He is President of STS International, a technology service firm he established in September 1985. His areas of technical interests cover static power conversion and optimal control systems as applied to industrial processes, energy conservation and energy management. He has been awarded 10 patents in this field and has published numerous technical papers.
Dr. Safiuddin is a Fellow ('93) of the IEEE and has served as Chairman of Industrial Controls Committee of IAS (1985-87), Chairman of Education Committee (1978-88), Director of the IEEE Buffalo Section (1983-86), and Chairman of the Industrial Utilization Systems Department of IAS (1990-91). He was awarded the Roscoe Allen Gold Medal in 1957 by Osmania University for excellence in the subject of hydraulics and was nominated for the prestigious B.G. Lamme scholarship of Westinghouse by his Division in 1968 and 1980. His contributions to industrial control technologies were recognized by the IEEE-Industry Applications Society by the "IUSD Award of Merit" for 1992 and the IEEE-EAB award for meritorious achievement in continuing education for the year 2000. He is a member of the Pi Mu Epsilon (Mathematics), Beta Gamma Sigma (Business) honor societies and an "Eminent Engineer" member of Tau Beta Pi (Engineering).
Thursday, 5th December, 2002 1730 hrs
"Trends in Mobile Communication and Broadband"
by Sanjeev Chachondia GM (Business Dev), Tata Broadband
Venue: Western Railway Conference Hall 2nd floor Old Building, Churchgate
Jointly with IETE, IRSTE, IEE, IEEE EMS Bombay Chapter

Thursday, 28th November , 2002 1500 hrs
"Micro/Nanotechnology in Biomedicine"
by Prof. Nitish Thakor , Department of Biomedical Engineering
The Johns Hopkins University School of Medicine , USA
Venue: EE Seminar Hall , IIT Powai, Mumbai 400 076
Jointly with AP/ED Bombay Chapter and EE Dept IIT Bombay
Abstract: Advances in micro and nanotechnologies are now finding wide spread applications in biomedical research and these technologies are penetrating even industrial and clinical practice. Excellent examples of research devices can be found in neuroscience research and examples of industrial devices can be found in gene expression and lab on a chip devices. My talk will review several methods, from simple ones that use microcontact printing to make sensors to more advanced ones that use photolithographic and nanofabrication approaches. I will focus on numerous advanced probes, sensors, and MEMS devices developed for neuroscience research. These include neurochemical and electrical sensors, microdrive mechansims and our latest work on nanosensors (all developed by various IIT grads and alumni!). The interface of brain research and micro/nanotechnologies is certainly a very fertile field for development and my talk will stimulate ideas for future projects, interdisciplinary work and collaborations.
Thursday, 31st October , 2002 1430 hrs
"Multiaccess in Cellular Systems with Multiple Antennas"
by Prof. Venu Veeravalli , ECE Department and Coordinated Science Lab , University of Illinois at Urbana-Champaign
Venue: EE Seminar Hall , IIT Powai, Mumbai 400 076
Jointly with Communcations Bombay Chapter
Abstract:Wireless systems in which multiple antennas are used at the transmitter and receiver (MIMO systems) have generated considerable interest in recent years. This talk will begin with a review of single antenna cellular systems and the traditional comparison of orthogonal multiaccess techniques (such as TDMA/FDMA) with non-orthogonal code division multiaccess (CDMA). The comparison is based on the achievable spectral efficiency in bits/s/Hz/cell. For delay-sensitive traffic (e.g., voice), the reasons for the alleged superiority of CDMA are discussed. The effect of using multiple antennas at the receiver and transmitter of the uplink is then considered in some detail. For fading channels, the spectral efficiency can be calculated based on ergodic or outage measures, and both measures are discussed. While the spectral efficiency calculation for orthogonal multiacccess with multiple antennas follows straightforwardly from a single user analysis, this calculation is considerably more complicated for CDMA. For the CDMA system, we will restrict our analysis to the case where the receiver performs single user decoding that follows possible multiuser detection. Our calculations indicate that the superiority of CDMA continues to hold with multiple antennas, and is in fact considerably more pronounced. For example, with one transmit antenna and a sufficient number of receive antennas, the (ergodic) spectral efficiency of CDMA with just single-user matched-filter detection is better than that of orthogonal multiaccess, even on a single cell basis. We also argue that transmit diversity does not improve the spectral efficiency of the CDMA system significantly. We end by commenting on the usefulness of space-time coding when combined with CDMA on the uplink.
Biography: Venu Veeravalli received the Ph.D. degree (1992) from the University of Illinois at Urbana-Champaign, the M.S. degree (1987) from Carnegie-Mellon University and the B. Tech. degree (1985) from the Indian Institute of Technology, Bombay, (Silver Medal Honors), all in Electrical Engineering. He joined the University of Illinois at Urbana-Champaign in 2000, where he is currently an Associate Professor in the department of Electrical and Computer Engineering, and a Research Associate Professor in the Coordinated Science Laboratory. His research interests include mobile and wireless communications, detection and estimation theory, and information theory. Dr. Veeravalli is currently an Associate Editor for IEEE Transactions on Information Theory, and an Editor for Communications in Information and Systems (CIS). Among the awards he has received for research and teaching are the IEEE Browder J. Thompson Best Paper Award in 1996, the National Science Foundation CAREER Award in 1998, the Presidential Early Career Award for Scientists and Engineers (PECASE) in 1999, and the Michael Tien Excellence in Teaching Award from the College of Engineering, Cornell University in 1999. He is a Beckman Associate at the Center for Advanced Study, University of Illinois for 2002-2003 academic year.
Wednesday, 30th October , 2002 1700 hrs
"Informal Meeting with Communications Society Members"
with Prof. Venu Veeravalli , ECE Department and Coordinated Science Lab , University of Illinois at Urbana-Champaign
Venue: Microelectronics Conference Room, IIT Powai, Mumbai 400 076
Jointly with Communcations Society Bombay Chapter

Tuesday, 29th October , 2002 1545 - 1700 hrs
Intel Distinguished Lecture Series "Building the Wireless Tomorrow"
by By Patrick Gelsinger , Vice President & Chief Technology Officer , Intel Corporation, USA
Venue: P C Saxena Auditorium, IIT Bombay, Powai, Mumbai 400076
Jointly with Intel Corpn, IIT Bombay
About the lecture: Convergence will be complete when consumers and businesses everywhere are always on the net, and wireless is the primary way this will be achieved: VP & CTO of Intel Corporation, Pat Gelsinger on the convergence of computing and communications and the future of wireless. We are in the midst of rapid convergence of mobility, communications, and computing technologies, as the mobile communications industry moves further into the computing space. These and other technologies are what the Intel Research Council specialize in supporting, through research grants which look beyond current product lines and identify projects intended to advance the computing industry at large. In his lecture Pat will talk about these & other such emerging wireless phenomenon and the opportunities and challenges to make mobile, connected experiences mainstream and deliver benefit to tomorrow's digital societies. In particular, he will focus on Intel's vision of mobile computing, describing the technology challenges/opportunities from silicon to protocols and applications. He will also describe in this context, work at Intel - in the research labs as well as product groups on building the "wireless tomorrow "
About the speaker: Pat Gelsinger is Vice President and Chief Technology Officer of Intel Corporation. Gelsinger joined Intel in 1979, and has more than 20 years of experience in general management and product development positions. Gelsinger leads Intel's Corporate Technology Group, which encompasses many Intel research activities, including leading Intel Labs and Intel Research, and driving industry alignment with these technologies and initiatives. As CTO, he coordinates Intel's longer-term research efforts and helps ensure consistency from Intel's emerging computing, networking and communications products and technologies. Gelsinger holds six patents and six applications in the areas of VLSI design, computer architecture and communications. He has more than 20 publications in these technical fields, including "Programming the 80386," published in 1987 by Sybex Inc. He has been the recipient of numerous Intel and industry recognition awards.
Saturday, 26th October, 2002 1015 to 1600 hrs
Student Branch Meeting
Venue: SPCE, Andheri West, Mumbai 400 058

Monday, 21st October , 2002 1600 hrs
"Design of Embedded System on Chip for Reliability"
by Dr. Rajendra M. Patrikar, Institute of High Performance Computing, Singapore
Venue: EE Seminar Hall , IIT Powai, Mumbai 400 076
Jointly with AP/ED Bombay Chapter
Abstract:Reliability is one of the most important requirements for the embedded systems since these systems should run with little or no human intervention. Unlike desktop and server systems, embedded systems cannot ask for operator help when application encounters a problem. Due to this High Availability (HA) is one of the hottest topics for the embedded design. Although most of the reliability problems are related to device design and technology some of the failures such as single event upset can only be taken care at design stage. This talk will review some of these mechanisms and design techniques used to make these chips robust. Talk will also briefly cover some of the other projects in computational electromagnetics and electronics division at Institute of High Performance Computing.
Saturday, 19th October, 2002 10:00 AM-12:30PM
Workshop on "CDMA in Mobile Communication"
by Prof Abhay Karandikar
Free for students
Venue: IIT Powai, EE Dept
Activity of Communications Society Chapter of Bombay Section
Thursday, 10th October, 2002 1600 hrs
Talk on " CCD Imagers"
by Dr. J. N. Roy, Semiconductor Complex Ltd, Chandigarh
Free for students
Venue: EE Seminar Hall, IIT Powai, Mumbai 400 076
Jointly with AP/ED Chapter of Bombay Section and CPMT India Chapter
Saturday, 5th October, 2002
Workshop on "Perspectives on Risk Management"
Characterization and Forecasting of Project Risks - Analysis and Case Studies
Faculty: Dr.Tzvi Raz, Tel-Aviv University, Israel
              Dr.Anant Patwardhan, IIT Bombay
              Mr. Rajesh Venkat, Sterlite industries Ltd.
              Mr.Deepji Singhal, FICA
Venue: Taj Mahal Hotel, Mumbai
Activity of : Engineering Management Society Chapter
Cosponsors : IEEE Bombay Section, Tata Consultancy Services, SPJ Institute of Management & Research Download brochure riskmgmt.pdf
Saturday, 28th September, 2002 1100 hrs
Talk on "Photonic bandgap and Antennas"
by Prof Yiannis Vardaxoglou
Venue: EE Conference Hall, IIT Powai, Mumbai
Cosponsored by Communications Society Chapter of Bombay Section
Thursday, September 26th, 2002 1600 hrs
Lecture on "High Reliability Power System Design"
by Mr. Keene Matsuda, IEEE Distinguished Lecturer
Venue: EE Conference Room, IIT Bombay, Powai, Mumbai 400076
Jointly with IEEE PES/IAS Bombay Chapter
Abstract: Basic factors for a highly reliable power system design include the following:
This talk will discuss each of these concepts as they apply to real-life projects that had requirements for a highly reliable power distribution system. Without a high degree of reliability and redundancy, continued operation and safety of personnel and equipment would be at risk. In order to increase reliability, one simplistic approach would be to design added layers of redundancy and alternate paths of power to anticipate for failures. However, haphazardly adding power system components simply drives up the initial cost of building the system. In addition, the number of contingencies (or coincident failures) should be considered early on in the design. For instance, a triple contingency design approach would be to maintain or restore power to all loads during a single utility outage, while a fault occurs on the distribution switchgear bus, all while a distribution transformer is down for maintenance. Generally, an infinite source of money is usually not available and, therefore, prudent engineering application of proper design concepts is required in order to produce a cost-effective and reliable power system.
About the Speaker: Keene M. Matsuda is a senior electrical engineer in the Design and Construction group with CH2M HILL, an international consulting company located in Santa Ana, California. He has over 20 years of experience in the design of electrical power systems for a wide range of projects including medium and low voltage substations and distribution networks, ground grids, lightning and surge protection, engine-generator and cogeneration power plants, highway and tunnel lighting, mass transit, grade separations, intelligent transportation systems, wastewater treatment plants, airport runway and taxiway lighting and signage and airfield navigational aids for a Category II system. He uses sophisticated computer software to perform power systems analysis and calculations for load flow, short circuit, motor starting, and over-current protective device coordination. Previously, he worked for Pacific Gas &Electric and PB Power Inc. He holds a BSEE from the University of California at Berkeley and is licensed to practice electrical engineering in eight states. He is a senior member of IEEE and currently serves on the Power Engineering Society Governing Board as a regional representative for USA and Canada. He is a member of the IEEE/PES Working Group on Distributed Resources Integration, the Working Group on Lightning Performance of Transmission Lines, and the Working Group on the Lightning Performance of Distribution Lines. He left his heart in San Francisco when he moved to New York City and then to Southern California where he now enjoys living in Huntington Beach with his wife, Freda, and a golden retriever puppy, Chloe, and doesn't miss the harsh winters of the east coast.
Friday, 13th September, 2002 1730 hrs
Lecture on " Current Developments in Fibre Optics Technology"
by Prof John E Midwinter
Venue: W. Railway Conference Hall, HQ, Old Building (2nd Floor), Opp Churchgate Station, Mumbai
Jointly with IETE Mumbai Centre, IRSTE Bombay Chapter, IEE Bombay Centre, FOA
Friday, September 6th, 2002 1530 hrs
"Microwave Device and Circuit Modelling with Neural Networks"
by Prof. Sheila Prasad, Northeastern University, Boston, USA
Venue: Institute of Technology for Women (ITW), SNDT University, Juhu-Tara Road, Mumbai
Cosponsored with IEEE ITW Student Branch
Abstract: This talk will present the application of neural networks to microwave device and circuit modeling. The application of the Simulated Annealing (SA) algorithm and its advantage over conventional gradient optimization methods to device modeling will be presented. This will be followed by a discussion of the neural network application to enhance the capability of SA and an introduction to the use of the Hopfield network and some examples. The use of the Genetic Algorithm (GA) in microwave system modeling will conclude the talk.
About the Speaker: Sheila Prasad received her B. Sc. Degree from the University of Mysore and S.M. and Ph.D. degrees from Harvard University, USA. She has been on the faculty of the Department of Electrical Engineering, New Mexico State University, USA, The American University in Cairo, Egypt, Birla Institute of Technology and Science, Pilani, King Fahd University, Riyadh, Saudi Arabia. She is currently Professor in the Department of Electrical and Computer Engineering, Northeastern University, Boston, USA. She has also been a post-doctoral Research Fellow at Harvard University, Visiting Professor at the Birla Institute of Technology, Mesra, Visiting Research Scholar at the Indian Institute of Science, Bangalore. During sabbatical leaves, she has been a Visiting Scientist at the Centre for Materials Science and Engineering at the Mass. Institute of Technology, USA, and Visiting Professor at the Technical University of Budapest, Budapest Hungary and the Department of Solid State Devices and Circuits at the University of Ulm, Germany. She has performed research in the area of Electromagnetic Theory and Applications particularly Antennas for her doctoral research. Her present research interests are in microwave characterization and modelling of semiconductor devices and circuits and optoelectronic device characterization and modeling. She has also served in the TOKTEN Programme of UNDP. She is a Senior Member of the IEEE and of the Scientific Honour Society, Sigma Xi.
Thursday, September 5th, 2002 1430 hrs
" High Frequency Characterization of HBT's"
by Prof. Sheila Prasad, Northeastern University, Boston, USA
Venue: EE Conference Room, IIT Bombay, Powai, Mumbai 400076
Cosponsored with AP/ED Chapter of Bombay Section
Abstract: This talk will present an overview of the characteristics of heterojunction bipolar transistors at frequencies above 1 GHz. After a description of the transistor structure, measurements with the automatic network analyzer will be discussed and the use of these parameters to obtain an optimum equivalent circuit large signal and small signal model will be presented. Issues such as self-heating will be discussed and the transistor modeling to take this into account will be presented.
Saturday, July 20, 2002 1630 hrs
"Nano-FET Fluctuation Physics" by Dr. Renuka Jindal, Electron Devices Society Distinguished Lecturer
Distinguished Member of the Technical Staff
Agere Systems, Murray Hill, USA
Venue: EE Seminar Hall, IIT Bombay, Powai, Mumbai 400076
Activity of EDS Chapter of Bombay Section
Abstract: Following its first demonstration in 1960 at Bell Labs, the understanding of the intrinsic noise mechanisms in the MOSFET quickly followed. However, as technology improved, the discovery and understanding of a host of other noise mechanisms slowly evolved over time. In this presentation, we will introduce the concept of random noise and describe its manifestation in the context of the MOSFET structure. This includes channel thermal noise, gate-induced noise, gate resistance noise, substrate resistance noise, substrate current supershot noise, bulk charge induced transconductance reduction noise and channel hot carrier noise. We will also discuss changes in the device structure to improve the noise performance by suppressing the effects of the extrinsic noise mechanisms. This work has resulted in almost an order of magnitude improvement in the noise performance of these devices making them suitable for lightwave and wireless communication applications.
About the Speaker:
Dr. Jindal received the Ph.D. degree in Electrical Engineering from the University of Minnesota 1981. Upon graduation, he joined Bell Laboratories at Murray Hill, New Jersey. His experience at Bell Labs over these last 21 years has bridged both technical and administrative roles. On the technical side he has worked in all three areas of devices, circuits and systems. Highlights include fundamental studies of noise behavior of scaled sub-micrometer MOS devices and the design of high-performance GigaHertz Band RF integrated circuits. He has also been involved in the study of the physics of multiplication phenomena and low noise signal amplification and detection in terms of novel devices and circuits including optoelectronic integration. On the administrative side, Dr Jindal has developed and managed significant extramural funding from federal agencies and independent Lucent business units. He was solely responsible, in Lucent Technologies, for developing and deploying a corporate-wide manufacturing test strategy in relation to contract manufacturing. On the academic side, he established and taught an RF IC design courses at Rutgers University. He also participates in ABET activities as an evaluator for Electrical Engineering programs at institutions in the United States.
Dr. Jindal received the Distinguished Technical Staff Award from Bell Labs in 1989. In 1991, he was elected Fellow of the IEEE for his contributions to the field of sold-state device noise theory and practice. He was the Editor-in-Chief of the IEEE Transactions on Electron Devices from 1990 to 2000. In December 2000 he received the IEEE 3rd Millennium Medal. Currently he is publications chair for the IEEE Electron Devices Society and a member of the Electron Devices Society Advisory Committee and Executive committee.
Dr. Jindal is the Chapter Partner of all the EDS Chapters in India, and responsible for the initiation of the Bombay Chapter in 1999.
Friday, 31st May, 2002, 1600 hrs
"From Circuits to Packets - Moving telecom to the IP World" by Dr M V Pitke
Venue: TIFR , Colaba, Mumbai
Activity of Communications Society Chapter of Bombay Section
Abstract:Internet and IP based services have been the focus of networks and services all over the world. Attempts are being made to move the present circuit switched services to the new IP world, and creating new carrier class packet based services from narrow band telemetry to broadband, multimedia and 3G wireless. Serious difficulties arise in ensuring a good quality of service- QoS due to the basic difference in the characteristics of the modes of transport. This is further aggravated by the emergence and demand of several new innovative services. Management of these problems requires techniques for bandwidth and delay control, like the MultiProtocol Label Switching-MPLS, ability to handle streams, integrated network management and security. New architectures focus on Softswitches and Gateways, the basic building blocks of the Next Generation Networks-NGN. I plan to discuss these and related issues in my talk.
Tuesday, May 28, 2002, 10:00AM-5:00PM
One Day Tutorial: "CDMA FOR WIRELESS COMMUNICATIONS"
by Dr. Rodger Ziemer, Fellow IEEE
Program Director for Communications Research, National Science Foundation, USA
Professor of Electrical and Computer Engineering, University of Colorado, USA
Venue: KR School of Information Technology Auditorium, IIT Bombay, Powai, Mumbai 400 076
Activity of Communications Society Chapter of Bombay Section
About the Speaker: "Rodger E. Ziemer received the BSEE, MSEE, and Ph.D. degrees from the University of Minnesota in 1960, 1962, and 1965, respectively. After serving in the U.S. Air Force from 1965-1968, he joined the University of Missouri - Rolla in 1968 where he stayed until 1983, having been promoted through the ranks to Professor. He moved to the Electrical and Computer Engineering (ECE) Department of the University of Colorado at Colorado Springs in January 1984 where he served as Professor and Chairman of ECE until 1993 and then as Professor from September 1993 to the present. In August 1998, he went on leave to the National Science Foundation, where he continues to serve as Program Director for Communications Research. He has spent intermittent periods on leave or sabbatical to various universities and industrial concerns. His principal area of research interest is digital communications. He has authored and co-authored several well-known textbooks in the area of digital communications and applied probability. "

Abstract : The fundamental theory of code-division multiple-access (CDMA) communication systems will be presented, including an overview of spreading codes and their properties, an overview of direct-sequence spread-spectrum communication systems, and application to CDMA as applied to wireless communications. The application of CDMA to second-generation wireless systems will be reviewed, and third-generation wireless standards will be overviewed. Some speculation will be given on what fourth-generation systems will look like with this session ending with an open discussion period.
Individual Participant fees: IEEE members Rs 1200      Non IEEE members Rs 1500      Students Rs 500
Register for the Tutorial by sending in name, e-mail id and address of participants to following e-mail addresses. Fee to be sent as a local cheque drawn in favour of “IEEE Bombay Section” on receipt of confirmation of registration.
Dr. Abhay Karandikar    karandi@ee.iitb.ac.in
Ashok Jagatia   ashokj@ieee.org
Friday, 17th May, 2002 1730 hrs 34th World Telecommunication Day
Keynote Address on this year's ITU Theme
"ICT (Information & Communication Technology) For All - Empowering People to Cross the Digital Divide"
by Lt Gen Prakash Gokarn PVSM AVSM (Retd)
Venue: W.Railway Conference Hall, HQ, Old Building (2nd Floor), Opp Churchgate Station, Mumbai
Jointly with IETE Mumbai Centre, IRSTE Bombay Chapter, IEE Bombay Centre
Saturday 23rd March 2002
"Results of Year 2002 IEEE Bombay Section Student Paper and Project Contest"
"Year 2002 IEEE Bombay Section Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
Friday, 15th March, 2002 1030 hrs
Lecture on "Silicon Technology trend from Past to Future - Downsizing from Millimeter to Nanometer"
by Prof. Hiroshi Iwai, Tokyo Institute of Technology, IEEE EDS Distinguished Lecturer
Venue: EE Seminar Hall, IIT Bombay, Powai, Mumbai 400076
Activity of AP/EDS Chapter of Bombay Section
Abstract: Information Technology (IT) is expected to greatly improve the quality of our life by making our society very efficient. It should be noted that the progress of IT entirely owes to that of semiconductor technology, especially, to that of silicon. Silicon integrated circuits provide us high speed/frequency operation of tremendously many functions with low cost, low power, small size, small weight, and high reliability. Progress of silicon integrated circuit has been driven by the downsizing of its components such as MOSFETs. In this talk, downsizing for silicon device technology is explained from the past to future. Especially downsizing into sub-100 nm is presented in detail. Finally, further challenge into sub-10 nm regime is mentioned.
About the Speaker: Prof. Hiroshi Iwai is one of the leading experts on CMOS technology in the world. After graduating from Tokyo University, he spent more than 25 years with Toshiba Corporation, working on important developments on MOSFET physics, CMOS technology, oxide scaling, and RF CMOS. Prof. Iwai's group at Toshiba demonstrated the first sub-50 nm MOSFET technologies in the early 1990's. Since 1999, Prof. Iwai has been a Professor at the Tokyo Institute of Technology. Professor Iwai is a Fellow of the IEEE, and a Distinguished Lecturer of the IEEE. His numerous awards include the Grand Prize of Nikkei BP Technology Awards (1994), the IEEE Paul Rappaport Award (1994), and the IEEE J.J. Ebers Award (2001) for "outstanding technical contributions to electron devices".
Friday, 8th February , 2002 1500 hrs
Lecture on "CMOS Digital VLSI Design - A Perspective"
by Prof. W S Khokle
Emeritus Professor, VRCE, Nagpur & Ex-Director, CEERI, Pilani
Venue: Sardar Patel College of Engineering (SPCE) ,Munshi Nagar, Andheri (W), Mumbai Tel: 6232192
Jointly with IEEE Student Branch of SPCE
Abstract:
ABSTRACT VLSI design methodology is being extended to cover newer areas such as networking applications, special processors, and sytem-on-chip etc. Various steps in the VLSI design procedure will be explained. Simple examples of digital logic and sequential circuits will be given. The trends and the advancement in some of the application areas will be presented. New designs with added features lead to increased complexity, power dissipation, and constraints on speed requirements. Some of the options and related tradeoffs to meet these requirements will be discussed.
Thursday, 7th February , 2002 1600 hrs
Lecture on "Electronic Design Towards Consciousness "
by Prof. W S Khokle
Emeritus Professor, VRCE, Nagpur & Ex-Director, CEERI, Pilani
Venue: Electrical Engg Seminar Hall, IIT Bombay, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
ABSTRACT There is considerable interest in understanding and emulating electronically the human brain-mind system due to the possible applications in medical treatment (such as of epilepsy) and in robotics etc. On the lines of development of AI systems, there is an effort to develop electronic systems with Artificial Consciousness (AC). Though the term may not be well-defined, it can encomapss a wide variety of capabilities such as awareness about existing capabilities (in sensing and their interpretation based on past experience), about objectives and choice of best approach to achieve it, about conflict detection and resoultion etc.
The talk will cover the basic building block - the electronic equivalent of biological neuron, the behaviour of neuron assemblies in response to external stimuli and internal signals. Attempts to design micochips to resemble performance of biological system will be presented. The internal system is to be designed so as to respond to the external inputs and environment as well as to get modified to record (store) the changes in the previous states. The next response to the external stimuli is affected by the modified internal system. Some of the models to achieve these will be presented. Self-awareness arising out of self-reference in the internal neural assemblies may lead to realisation of higher levels of consciousness as in the brain-mind complex. Some of the characteristic fearures of the human complex and the aspects which can be possibly be modelled will be discussed.
Fri-Sun, 25-27 January 2002
"National Communications Conference 2002 "
Website : http://www.ee.iitb.ac.in/~NCC2002/
Co-sponsored by IEEE Bombay Section
Tues-Wed, 22-23rd, January 2002
Two day seminar on "Electrical Safety in Industries"
Venue: Electrama Exhibition at Goregaon East , Mumbai.
Activity of PES/IAS Chapter of Bombay Section
Contact for registration: Mr. D.M. Tagare, Chairman, PES/IAS Bombay Chapter,
IEEE Bombay Section, 106/2A Senapati Bapat Road, Pune 411016, India.
Tel: +91-20-7122360 E-Mail: mcpl@pn2.vsnl.net.in
Monday, 21 January 2002, 1600 hrs
Lecture on "Common Sense and Knowledge Approach to Electrical Safety"
by IEEE IAS Distinguished Lecturer, Dr. Bruce L. McClung
Venue: Conference Room, Dept of Electrical Engg , IIT , Powai, Mumbai 400 076
Activity of IAS Chapter of Bombay Section
Dr. Bruce L. McClung, an internationally renowned figure in electrical safety, is a Distinguished Lecturer of the IEEE Industry Applications Society. He became a Fellow of the IEEE in 1989. He is also the recipient of the IEEE Standards Medallion Award, the Charles Proteus Steinmetz Award, and the IEEE Medal for Engineering Excellence.
Saturday, January 5, 2002, 10:00AM-1:00PM
Half Day Workshop: "Innovate or Evaporate: Reviving the Entrepreneurial Spirit Among India's Elites"
by IEEE EDS Distinguished Lecturer, Professor Vijay K. Arora
Department of Electrical and Computer Engineering, Wilkes University
Wilkes-Barre, PA 18766, USA
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section , GOLD Program , and the E-cell at IIT Bombay
The planet Earth is moving into multinational companies, strategic alliances, and markets for resource utilization that see no geographical barriers. These international collaborations are creating a dire need for renaissance professionals-skillful and ingenious masters of engineering, economics, and human motivation-those who have vision beyond the confines of their disciplines, organizations or nations. This workshop considers this shift in paradigm and presents heuristics to revive the entrepreneurial spirit by synthesis of ideas from engineering and behavioral sciences, thereby capitalizing on and contributing to the creativity of India's elites. Creativity is busting the conventional mental blocks and playing with imagination and possibilities, leading to new and meaningful connections and outcomes while interacting with ideas, people and the environment. New paradigms to engineer the direction of the organization you work for, will work for or create one for others to work for are suggested. The attendees will learn to dive for knowledge in the information pool and learn to swim to create a product, procedure or plan that will be of value to the community one lives in, no matter where in the world.
Friday, 4th January, 2002 1500 hrs
Lecture on "Hot Electrons: A Myth or Reality?"
by IEEE EDS Distinguished Lecturer, Professor Vijay K. Arora
Department of Electrical and Computer Engineering, Wilkes University
Wilkes-Barre, PA 18766, USA
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
A review of steady-state electronic transport in a high electric field is given. In particular, expressions for mobility and diffusion-coefficient degradation are obtained in the framework of asymmetric distribution function [1]. The concept of a hot electron and its temperature in a given context is discussed and simple analytical expressions extracted. These contextual definitions include: energy temperature, mobility temperature, Einstein-relation temperature both under ac and dc conditions, quantum temperature, and two-band intrinsic temperature. The dependence on the electric field is given in each case and the role of electric-field-induced quantum emission is delineated. [1] Arora, V. K., Microelectronic Journal, Quantum Engineering of Nanoelectronic Devices: The Role of Quantum Emission in Limiting Drift Velocity and Diffusion Coefficient, 31 853(2000).
Thursday, 3rd January, 2002 1430 hrs
Lecture on "Growth in Power Microelectornics - A Market Perspective"
by Prof. Shankar N. Ekkanath Madathil
De Montfort University, UK
Venue: Conference Room Dept of Electrical Engg, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
The legislated stringent requirement of energy savings in every walk of life demands more efficient power systems. In response, power semiconductor manufacturers world-wide are focussing on the development of high performance power semiconductor devices and ICs. The world market for power semiconductors has grown from $4.94 billion in 1996 to $11 billion in 2001 and is expected to increase with a CAGR of 10% over the next few years. Power semiconductor devices belong to a separate segment of the semiconductor market, differing both in production technology and end-user applications. The power semiconductor industry, in contrast to the low voltage integrated circuit sector with its handful of major mass producers, has still room for smaller industries with innovative, differentiated products. This is because, 70-80% of the power semiconductors are sold directly from the manufacturer to the end user and distribution networks account for the rest. The net successful outcome is set to result in more competitive, highly reliable, and more energy efficient power electronics equipment. Development of innovative, highly differentiated products through smaller power semiconductor manufacturing industries will increase their market share and improve the profitability of the electronics industry. The major driving force for advancing power microelectronics is to achieve cleaner environment through efficient power systems; more efficient use of sustainable resources and added value; and, improve the overall quality of life. In Electric vehicles using fuel cell or hybrid approach, a more efficient inverter is essential and the developments will improve the inverter performance significantly. The photovoltaic systems can also benefit from inverters that are more efficient. The increased reliability of the products can increase the safety aspects of the traction systems. The performance gains will directly reflect in efficiency improvements in automotive, computers, office equipment, consumer electronics, industrial, military & aerospace, communications and consumer white-goods manufacturers, to name a few.
This talk will cover the market issues and advances in power microelectronics, which spans Discrete, Intellgient Power Chips and Power Integrated Circuits. Recent progresses in Diodes, Super Junction Devices, IGBTs to new concepts such as the Clustered IGBT will be covered. Technology advancements such as the Non-Punch-through technology and Field Stop technologies will be highlighted.
The demand for Industry/Academic co-ordinated efforts to advance power microelectronics in India will be identified, which will form the basis for an open discussion.

About the Speaker: Prof. Shankar N Ekkanath Madathil is currently employed as a Research Manager in the Emerging Technologies Research Centre, De Montfort University. He has many years of experience in the field of solid state microelectronics. He has published more than 100 papers within this broad area and has several patent applications pending approval in the area of semiconductor devices. The devices proposed have been cited in textbooks and leading journals.
Prior to joining DMU, he was elected to work as a Maudslay Engineering Research Fellow at Pembroke College, Cambridge (1991-1994) and a Research Associate at the Cambridge University Engineering Department (1993-1994). He joined Cambridge University as a Ph.D. student from India under the prestigious Nehru scholarship in 1987. As a Ph.D. student, he worked to initiate the pioneering research in the area of high voltage integrated circuits within the UK community. The HV-CMOS process developed by him is currently used in Fuji Electronic, Japan and in the UK. In 1994, he was elected to a Senior Stokes Fellowship in Pembroke College.
The Emerging Technologies Research Centre, which he set-up in 1995 within a 'New University' has now grown significantly within a short span of time. This Centre has been strategically positioned to attract funding from both industries and academic grant awarding agencies. The research culture of the Centre is based on team-work & quality at international level. Prof. Ekkanath has been acting as a consultant to UK based semiconductor industries. More recently, he has been awarded in excess of £2.5 Million pounds by EPSRC and industries for rapid commercialisation of advanced power devices through strategic alliances with major, international power semiconductor industries based in the USA, UK and other countries. He is a Senior Member of the IEEE and a member of AMBA for the last four years. He is a sub-committee member of the IEEE-ECTC conference in the area of components & RF. He has been awarded the premier BBV Foundation Award from Spain to spend some time as a Visiting Professor at CNM, Spain during the year 2000. More recently, he has been invited to serve as a selection committee member of the EU funded Microserv program, which is part of the EC-Human Potential Access to Research Infrastructure Action program. He has been invited to be part of the International program committee of the IEEE & IEE Co-sponsored International Symposium of Power Semiconductors in Prague, IEEE Co-sponsored International Conference on Microelectronics in Nis, Yugoslavia.
The reason for his visit to India is to identify and seek potential collaborative partners to advance power microelectronics in India.
Saturday 29th December, 2001 1530 hrs
Lecture on "Semiconductor Quantum Nanostructures : Nature's way"
by Professor Anupam Madhukar
University of Southern California USA
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
Self-organization in Nature is a fundamental paradigm that can serve well the thrust towards realization of arrays of semiconductor quantum nanostructure s that are unlikely to be obtained through the conventional paradigm of carving on ever finer length scales. In this talk I shall touch upon some of the emerging self-assembly approaches to nanostructure synthesis and focus on surface stress driven assembly of semiconductor quantum dots and their potential for Optoelectronic (laser, photodtectors, etc.) Electronic (few and single electron) devices.

About the Speaker: Professor Anupam Madhukar Kenneth T. Norris Professor of Engineering Professor of Materials Science and Physics Director, Center for Intelligent Manufacturing of Semiconductors (CIMOS) Member, Laboratory for Molecular Robotics (LMR) Dr. Madhukar received his BSc (1966) and MSc (Physics, 1968) degrees respectively, from the University of Lucknow and the Indian Institute of Technology (Kanpur) in India. He received his Ph.D. in Materials Science and Physics in 1971 from the California Institute of Technology. Before coming to USC in 1976, Dr. Madhukar was a Post Doctoral Research Fellow at the Thomas J. Watson Research Center of the IBM Corporation and a Research Associate at the James Frank Institute of the University of Chicago. Dr. Madhukar was an Alfred P. Sloan Fellow (1977-81), received three NASA Certificates of Recognition (1981, 1982, 1986) for his research in Si/SiO2 interfaces and compound semiconductor MBE, Outstanding Research Award of the USC School of Engineering in 1988, and the DARPA (ETO) award for Sustained Excellence, 1997 (given to a multidisciplinary team lead by Dr. Madhukar). He is the founding President of the Southern California chapter of the Materials Research Society and a member of the New York Academy of Sciences.
Wed - Fri 26 - 28th December, 2001
"International Conference on Quality, Reliability and Control (ICQRC-2001)"
Venue: Hotel Le Royal Meridien, Mumbai
For details, please contact :
Prof. T. S. Rathore tsrathor@ee.iitb.ac.in
Website : www.iitb.ac.in/~iete/
Tuesday, 18th December, 2001 1615 hrs
Lecture on "Optical Networking with IP over DWDM : Recent Advances, Trends and Issues"
by Prof. Raj Jain, Fellow IEEE , Distinguished Lecturer, IEEE ComSoc
Co-founder & CTO - Nayna Networks, USA
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of Communications Society Chapter of Bombay Section
"Annual General Body Meeting"... Notice...Saturday 15th December 2001
- Slate given by Nominations Committee
- RSVP Letter of Acknowledgement
- Newsletter
- Secretary Report for the year 2001
- Events in 2001
Thursday, 13th December, 2001 1500 hrs
Lecture on "Physical Analysis of Ultra Thin Gate Oxide Breakdown"
by IEEE EDS Distinguished Lecturer, Dr. M. K. Radhakrishnan, Singapore
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
Device failure mechanism study is very important in understanding and enhancing the reliability irrespective of the technology limitations. Building in Reliability in devices starts with the design and strengthen through process and testing. The most important aspects of the failure mechanism study are the fail site identification and physical analysis, which becomes a challenge as the technology advances to deep sub-micron regime. The trends in the physical analysis studies to understand the reliability degradations in the latest technology involving ultra thin gate oxides (25-30A) are discussed in this talk. The physical analysis of soft breakdown in these ultra thin gate oxides have been demonstrated to correlate with the electrical failure characteristics. Eventhough reviews on the physical models of thin gate oxide reliability are available, establishing failure mechanisms by physical analysis of device structures is complex and difficult. The direct observation of the breakdown failure mechanism for functional devices is discussed and illustrated using transmission electron microscopic analysis. Effect of stressing on barrier layers as well as gate structure is explained with the physical analysis results. Specific analytical methods such as Focused Ion Beam and Transmission Electron Microscopy used for such physical analysis are explained in view of their significance in establishing the mechanisms to understand the reliability concerns.
Saturday, 8th December, 2001, 1500 hrs
IEEE Bombay Section SILVER JUBILEE Function
Venue: Hotel Le Royal Meridien, Sahar Airport Road, Andheri(E), Mumbai 400 059 ( Tel: 838 0000)
- 1500 to 1615 hrs Lecture by Prof. Kesav V Nori, Tata Consultancy Services, Mumbai
  "Differences & Similarities between Software Engineering and other Engineering Disciplines"
- 1615 to 1730 hrs Lecture by Prof. Rajesh Gupta, IEEE Ckts & Sys Soc. Distinguished Lecturer Dept. of Computer Science, University of California, Irvine
  "Design Technology and Architectural Adaptation for Deep Sub-micron VLSI Systems"
- 1730 hrs High Tea
Abstract of lecture on :"Design Technology and Architectural Adaptation for Deep Sub-micron VLSI Systems"
We present an assessment of the technology trends and its implications for the computer systems architecture and design tools for the coming generations of process technologies. Based on technology projections from the SIA road-map, the cumulative effect of continuing increases in interconnect delay relative to gate switching would fundamentally alter the ground rules in the design of high performance circuit blocks and the role of interconnect between the circuit blocks. For instance, multiple storage elements could be located in a cycle period whereas block-level interconnect would no longer be a part of the cycle time. Architecturally, increased local decision making can be used to adapt a data-path to application-specific computational requirements. To illustrate how this adaptability can be used in efficient system architectures, we present highlights from the study of latency-hiding mechanisms to improve the interaction of processing and memory elements as a part of the on-going DARPA-sponsored project on high-performance data-intensive embedded computing. From a design technology standpoint, language-level modeling and system co-design of hardware/software blocks under strict timing constraints present a special challenge to the next generation of system design tools. The new design technology must balance increasing technology dependence while advancing the level of abstraction towards target applications. I will present an overview of our work system-level CAD algorithms and describe how system design problems are addressed in a framework that allows the system architect to interactively explore intelligent design options without leaving the application development environment. This talk describes on-going research activity. We welcome participation and feedback from the audience.
Saturday, 8th December, 2001 1100 hrs
Lecture by Arun K Somani, David C. Nicholas Professor ,
3227 Coover Hall, Dept. of Elect. and Comp. Engr., Iowa State University, AMES, IA 50011,
Email: arun@iastate.edu
"Beyond SONET and SDH: Challenges and Issues"
Venue: Dept of Electrical Engg Conference Room, IIT , Powai, Mumbai 400 076
Activity of CS Chapter of Bombay Section
Abstract:
SONET has played an important role in the design and operation of a number of networks around the globe. However, it is fast approaching its limits. SONET was originally built for transporting 64-kbps voice channel traffic. It is not exactly suited for the efficient transport of Internet related data traffic. In addition, bandwidth scaling difficulties, quick provisioning and the need for service differentiation necessitates the need to leverage traditional SONET/SDH to newer technologies. We will examine some of the issues that need to considered in the evolution of SONET/SDH to newer network technologies that uses wavelength-division multiplexing-based optical networking technology. We will address issue related to traffic grooming to support IP over WDM, satisfy demands for different Quality of Service (QoS), and survivability issues in WDM-based networks.
Mon-Fri 3rd - 7th December, 2001
"International Conference on Broad-Band Optical Fibre Communication Technology (BBOFCT-2001)"
Venue: University of North Maharashtra, Jalgaon
For details, please contact :
Prof. D. K. Gautam dkgautam_nmu@hotmail.com
Website : www.nmu.ac.in/BBOFCT-2001.htm
Monday, 3rd December, 2001 1100 hrs
Lecture on "Wideband and Low Voltage Waveguide Modulators with Asymmetric Coupled Quantum Wells beyond 40 Gb/s"
by IEEE EDS Distinguished Lecturer Dr. Kunio Tada, Fellow IEEE,
Professor Emeritus,
Department of Electrical and Computer Engineering,
Graduate School of Engineering
Yokohama National University, Tokiwadai 79-5, Hodogaya-ku, Yokohama, 240-8501, Japan
tada@dnj.ynu.ac.jp, Phone/ fax: 45-339-4274
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
The five-layer asymmetric coupled quantum well (FACQW) is expected to show very large electrorefractive index change in a wideband transparency region far from the absorption edge. In an early stage of the study, a Mach-Zehnder interferometer traveling-wave type modulator with the FACQW obtained the modulation bandwidth of 55GHz and the switching voltage of 3 V. In order to realize ultrafast, ultralow voltage, and wideband optical modulators, improvement in growth of the FACQWs is being pursued. In addition, the migration enhanced epitaxy method is being tried for a better heterointerface flatness and a reduced growth temperature.
Monday, 26th November 2001 1500 hrs
Seminar by Dr. Cor Claeys, IEEE Distinguished Lecturer, Inter-University Microelectronics Centre (IMEC) Leuven, Belgium
"Technology Roadmap Challenges for Deep Submicron CMOS "
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
The ultimate downsizing of the minimum feature size is hampered by physical, technological and economical limitations. To ensure Moore's law below 100 nm technology nodes both front- and back-end processing has to face technological challenges as clearly stipulated by the International Technology Roadmap for Semiconductors (ITRS). Lithography, gate stack, shallow junctions, high- and low-k dielectrics and interconnect schemes are nowadays amongst the hot research issues leading to a global collaboration. This presentation reviews some of the on-going research efforts to come to cost-effective solutions forming the backbone for future technology generations. The link between micro- and nano-electronics is also addressed.
BIOGRAPHY OF SPEAKER: Cor Claeys was born in Antwerp, Belgium. He received the electrical engineering degree in 1974 and the Ph.D. degree in 1979, both from the Katholieke Universiteit Leuven (KU Leuven), Belgium. His doctoral research was in the field of process-induced defect characterization for VLSI technologies. >From 1974 to 1984 he was, respectively, Research Assistant and Staff Member of the ESAT Laboratory of the KU Leuven and is, since 1990, Professor. In 1984, he joined IMEC, Leuven, as Head of the Silicon Processing Group. Since 1992, he has been responsible for technology business development. His main interests are in general silicon technology for ULSI, device physics including low-temperature operation, low frequency noise phenomena and radiation effects, and defect engineering and material characterization. He co-edited a book on Low Temperature Electronics and has authored and co-authored six book chapters and more than 400 technical papers and conference contributions related to the above fields. Dr. Claeys is a member of the Electrochemical Society, SEMI, the European Material Research Society and a Senior member of IEEE. He is an associate editor for the Journal of the Electrochemical Society. Within IEEE he is presently elected AdCom member of the Electron Devices Society, Chair of the IEEE Benelux Section, Chair of the Benelux ED Chapter and coordinator for ED Chapters in Region 8. In 1999 he has been elected as Academician and Professor of the International Information Academy.
Mon Tues, 26-27th November, 2001
Seminar on "DSP VLSI Design and Applications (DVDA-2001)"
Venue: University of Pune, Pune
For details, please contact :
Prof. S. V. Ghaisas info@icitonline.org
Tuesday, 6 November 2001, 1600 hrs
Lecture by Dr M V Pitke , Fellow IEEE
"WIRELESS AND THE INTERNET"
Venue: Lecture Hall, BSES Telecom Ltd, E-7 MIDC Area, Andheri East, Mumbai - 400 093.
Contact Person: Mr Rajiv Bhaduria, BSES Telecom, Tel No 825 6435
Activity of ComSoc Chapter of Bombay Section

Tuesday, 27th October, 2001
One Day Workshop on Microelectronics
- Inaugural Speech (10 minutes) - Prof. A.N.Chandorkar
- The Microelectronics Revolution ( 1 hour)- Prof. V.Ramgopal Rao
- MOS Circuit Design in the ULSI Era ( 1 hour)- Prof. A.N. Chandorkar
- Design of Multi-million Transistor ULSI Chips (1 hour)- Prof. D.K.Sharma
- VLSI Circuit Simulations (1 hour)- Prof. Mahesh Patil
- Integrated Circuit Fabrication ( 1hour)- Prof. V.Ramgopal Rao
Venue: Fr.C.Rodrigues Institute of Technology, Vashi, New Bombay
Activity of AP/ED Chapter of Bombay Section and IETE
Microelectronics Workshop:
Throughout the past four decades, both the productivity and performance of microelectronics have advanced at exponential rates unmatched in technological history. The number of transistors per microchip has skyrocketed by a factor of about 100 million, while the cost of a chip has remained virtually constant. And the amount of energy consumed in a binary switching transition has been reduced by more than five decades! Consequently, microelectronics has become the principal driver of the modern Information Revolution. And the ubiquitous microchip has had a profound and pervasive impact on our daily life. The current minimum dimension on chip can be as small as as 0.1 micrometers in width, or 1/1,000th the width of a human hair. What made this Microelectronics revolution possible, how is it all done, what lies ahead, and what kind of systems will be prevailing in the year 2010? This Workshop on Microelectronics, being conducted by the Microelectronics group, IIT Bombay will address some of the above questions, and is an excellent opportunity to know more about this field. Microelectronics group at IIT Bombay is one of the most active groups in the country and some of the contributions from this group are recognized the world over. This is an excellent opportunity to interact with them and know more about this field.
For more information, please contact Mr. K. T. V. Reddy ktvr@ee.iitb.ac.in
Tuesday, 16th October, 2001, 1500 hrs
Seminar by Dr. Rajendra Patrikar, Institute of High-Performance Computing, Singapore
"Physical Design Engineering Activities at Institute of High-Performance Computing"
Venue: Dept of Electrical Engg Seminar Hall, IIT , Powai, Mumbai 400 076
Activity of AP/ED Chapter of Bombay Section
Abstract:
During the process of designing high-performance VLSI circuits, designers often find that their silicon implementations do not meet the timing and/or area constraints. Post-layout verification tools have been in use for some time to solve this problem. The basis of these tools is modelling of inteconnect structures. It appears that various physical effects arising out of VDSM technology need to be modeled accurately to predict the circuit element behaviour. One such effect is roughness on interconnects and other circuit elements. ECAE division at IHPC is working on post-layout tools for some time. Recently we have also started work on surface roughness modeling. The talk will also cover our research projects in the area of Test on Chip and Chip Planning Tool for SOC design environment
Thursday, October 4, 2001 , 1700 hrs
Lecture by Dr. Ashok Jhunjhunwala , IIT Madras
"Towards Enabling India through Telecom and Internet"
Venue: Thadomal Shahani Engineering College, Bandra, Mumbai 400050
Biography of the Speaker:
Dr. Ashok Jhunjhunwala is Professor and Head of the Department of Electrical Engineering at IIT Madras. Dr.Jhunjhunwala leads the team that developed corDECT, India's indigenous Wireless Local Loop technology that's winning accolades the world over. His research interests span Telecommunications, Computer Networks and Fibre Optics, and he's particularly active in developing cost-effective wireless telecommunications solutions. The Wireless Local Loop system developed in his lab today is being deployed in Argentina, Brazil, Tunisia, Madagascar, Kenya, Angola, Nigeria, Yemen, Fiji and Iran besides India. The corDECT Wireless in Local Loop provides 35/70 Kbps Internet and simultaneous voice conversation at a cost much lower than that of any other WLL product. Digital Internet Access Switches (DIAS) is a DSL on copper product providing 144 Kbps or 2 Mbps Internet plus simultaneous voice. optiMA Fibre in the Loop system provides SDH fibre back-haul and lowest cost telephony The current mission that Dr.Ashok Jhunjhunwala leads is to enable every village of India to have telecom and Internet connections. Recognising that Internet is power, Dr.Jhunjhunwala and his colleagues have helped formation of the operators company n-Logue Communications Pvt. Ltd., focussed on providing telephone and Internet in every village. The work to provide such connections is going in Madurai and Cuddalore District of Tamil Nadu, Dhar district of Madhya Pradesh and Sikar district of Rajasthan. The objective is to provide 1 million connections in Indian small towns and rural areas in the next three to three and a half years. Dr. Jhunjhunwala is a fellow of INAE, INSA. Indian National Academy of Science, and Governor of International Council for Computer Communications. He is on the Board of Directors of several companies, including Sasken Communications Ltd., Bangalore, Banyan Networks Pvt. Ltd., Chennai, Polaris Software Lab Ltd., Chennai, and n-Logue Communicatons Pvt. Ltd., Chennai. Dr. Jhunjhunwala has received many awards and accolades, among them: 1st Prof.S.N.Mitra Memorial Award, IETE, Dr.Vikram Sarabhai Research Award for the year 1997 towards the contributions and achievements in the field of Electronics, Informatics, Telematics & Automation, the Shanti Swarup Bhatnagar Award for outstanding contributions in the field of Engineering Sciences for the year 1998. And the Distinguished Alumnus award by IIT Kanpur.
Tuesday, 25th September, 2001, 1600 hrs
Lecture by Dr Abhay Karandikar, IIT Mumbai
"Demystifying Multi-Protocol Label Switching (MPLS)"
Venue: Lecture Hall, BSES Telecom Ltd, E-7 MIDC Area, Andheri East, Mumbai - 400 093.
Contact Person: Mr Rajiv Bhaduria, BSES Telecom, Tel No 825 6435
Activity of ComSoc Chapter of Bombay Section

Saturday, 8th September, 2001
One day Wokshop on "Advances in Microelectronics"
Venue: University of Pune
Activity of IEEE Bombay Section and AP/ED Chapter of Bombay Section
About 240 participants, including students, faculty members and personnel from VLSI training centres, attended the workshop and interacted with the speakers.
Picture of the Wokshop

Wednesday, 5th September, 2001, 1600 hrs
Lecture by Guru Hariharan, Chief Executive, BSES Telecom Ltd
"Developments in Satellite Communication and Broadband Internet"
Venue: Lecture Theatre, BSES Telecom Ltd, E-7 MIDC Area, Mumbai - 400 093.
Activity of ComSoc Chapter of Bombay Section

Monday, 3rd September, 2001, 1030 hrs
Lecture by R. Ramakumar, Fellow, IEEE PSO/Albrecht Naeter Professor and Director, Engineering Energy Laboratory School of Electrical and Computer Engineering Oklahoma State University
"Integrated Renewable Energy Systems (IRES)"
Venue: Dept of Mechanical Engg Seminar Room, IIT Powai, Mumbai 400 076
Abstract:
One of the greatest challenges facing the scientific and technical communities of the world is to meet the expectations of humanity and contribute to global development in a sustainable manner in the context of burgeoning global population with increasing expectations. Energy is a key player in facing this challenge, Harnessing locally available renewable energy resources to "energize" rural areas, if properly planned and executed, is the most logical approach from both environmental and economic points of view. IRES provide the key to this approach. IRES utilize two or more renewable energy sources and end-use technologies to supply a variety of energy and other needs. It has multiple inputs in different forms and quality. It also has multiple outputs in different forms and quality. Designing IRES involves finding the ratings of the energy conversion and energy storage devices required to satisfy a variety of energy and other needs utilizing locally available renewable energy resources. This seminar will discuss the design considerations and design tradeoffs involved and a knowledge-based approach to the design of IRES.
Biography of Speaker: Dr. Ramakumar received his B.E. from the University of Madras, M.Tech. from IIT- Kharagpur, and Ph.D. from Cornell University, Ithaca, New York. He was associated with the faculty of Coimbatore Institute of Technology for 10 years before joining the Electrical Engineering faculty at Oklahoma State University in Stillwater, Oklahoma, USA. At present he is serving as the PSO/Albrecht Naeter Professor and Director of the Engineering Energy Laboratory. His research interests are in conventional and unconventional energy conversion, power engineering, energy storage, renewable energy, and engineering reliability. His work has been documented in more than 150 publications, including four US patents. He was elected Fellow of IEEE in 1994 for his contributions to renewable energy systems and leadership in power engineering education. Dr. Ramakumar's textbook entitled Engineering Reliability: Fundamentals and Applications, published by Prentice Hall in 1993 and its Asian edition have been adopted by more than a dozen universities in the US and by several universities around the world. He is the Chairman of the Energy Development Subcommittee and Chairman of the Working Group on Renewable Energy Technologies of the IEEE Power Engineering Society. In addition, he Chairs the Awards Committee of the Technical Council and participates as a member in several other Working Groups, Committees, and Subcommittees of the Power Engineering Society. He is a member of the American and International Solar Energy Societies, American Society for Engineering Education, and is a Professional Engineer in the State of Oklahoma.
Friday, 10th August, 2001, 1130 hrs
Lecture by Professor Robert W. Newcomb, Distinguished Lecturer of the IEEE Circuits and Systems Society(CAS), University of Maryland, USA
"Ear Type Systems"
Venue: EE Seminar Hall, IIT Powai, Mumbai 400 076
Abstract:
Ear type systems are ones which mimic the behavior of biological ears with iour emphasis upon vlsi realization. The systems under discussion use auto-emissions, often called Kemp Echoes, as noninvasive signals from which various 2-port and 4-port lattice models of the inner ear are developed to characterize the inner ear, in some cases through the transfer scattering matrix. From the resulting models vlsi circuits are obtained with various transistorized realizations available including CMOS switched current ones.
Biography of Speaker: Professor Robert W. Newcomb is a Professor at the University of Maryland, and a Life Fellow of the IEEE. He had his education at Purdue (BSEE), Stanford (MS) and Berkeley (Ph.D.). He was on the faculty at stanford University, and, since then, has been at the University of Maryland for more than 25 years, where he is Director of the Microsystems Laboratory. His wide research interests include analog VLSI, biomedical engineering, circuit and systems theory, microsystems, neural networks and robotics. Besides a large number of papers, he is the author of several books, including the well-known classic, "Linear Multiport Sysnthesis". He is the recipient of the Golden Jubilee Medal and the Education Award of the IEEE CAS Society. He is a Distinguished Lecturer of the IEEE CAS Society. He has been a Visiting Professor in Australia, Malaysia, Spain, Singapore and Korea.
Wednesday, 25th July, 2001, 1530 hrs
Lecture by Prof. Arye Nehorai , Chief Editor IEEE Trans. on DSP Signal Processing, Professor, Electrical and Computer Engineering Department, The University of Illinois at Chicago
"New Directions in Space-Time Information Processing "
Venue: EE Seminar Hall, IIT Powai, Mumbai
Abstract :
Temporal measurements of sensor arrays are used to estimate signal information in the presence of noise. I will first briefly survey my recent contributions to this area, including electromagnetic and acoustic vector-sensor processing, chemical sensor array processing, biomedical applications, and antenna arrays for communications. I will then focus on the case of electro- and magneto-encephalography (E/MEG) sensor arrays for detecting electric sources in the brain. These arrays measure electric potentials on the scalp and magnetic fields around the head. I will present maximum likelihood methods for estimating evoked responses, which allow for spatially correlated noise between sensors with unknown covariance. The electric sources will be modeled as current dipoles. I will estimate the unknown dipoles' locations and moments, and present Cramer-Rao lower bounds on their estimation errors. Numerical examples will be shown to illustrate the results for real data, including the accuracy to which sources can be localized in different regions in the brain.

Biography:
Arye Nehorai received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion-Israel Institute of Technology, in 1976 and 1979 respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1983. After graduation he worked as a Research Engineer for Systems Control Technology, Inc., in Palo Alto, CA. From 1985 to 1995 he was with the Department of Electrical Engineering at Yale University, New Haven, CT, where he became an Associate Professor in 1989. In 1995 he joined the Department of Electrical Engineering and Computer Science at The University of Illinois at Chicago (UIC), as a Full Professor. He is currently Chair of the department's Electrical and Computer Engineering Division and is managing the creation of a new ECE Department at UIC. He holds a joint professorship with the Bio-engineering Department at UIC. His research interests are in signal processing, communications, and biomedicine. Dr. Nehorai is Editor-in-Chief of the IEEE Transactions on Signal Processing. He is also a Member of the Publications Board of the IEEE Signal Processing Society and the Editorial Board of Signal Processing. He has previously been an Associate Editor of the IEEE Transactions on Acoustics, Speech and Signal Processing, of IEEE Signal Processing Letters, the IEEE Transactions on Antennas and Propagation, the IEEE Journal of Oceanic Engineering, and Circuits, Systems, and Signal Processing. He served as Chairman of the Connecticut IEEE Signal Processing Chapter from 1986 to 1995 and is currently the Chair and a Founding Member of the IEEE Signal Processing Society's Technical Committee on Sensor Array and Multichannel (SAM) Processing. He was the co-General Chair of the First IEEE SAM Signal Processing Workshop, held in 2000, and will serve in this position in 2002. He was co-recipient, with P. Stoica, of the 1989 IEEE Signal Processing Society's Senior Award for Best Paper. He received the Faculty Research Award from UIC College of Engineering in 1999. He has been a Fellow of the IEEE since 1994 and of the Royal Statistical Society since 1996.
Wednesday, 11th July, 2001, 1600 hrs
Lecture by Dr. Abhijeet V. Chavan
"MEMS: Design, Technology, and Fabrication"
Venue: EE Seminar Hall, IIT Powai, Mumbai
Activity of AP/ED Chapter of Bombay Section
Abstract:
Dr. Abhijeet V. Chavan is a Design Manager with Delphi Automotive Systems, affiliated with there Delco Electronics Division. He obtained his PhD from the University of Michigan, Ann Arbor. His primary area of development/research is silicon based MEMS and related CMOS/BiCMOS interface techniques. In the presentation scheduled for July 11 Dr. Chavan will present MEMS development by discussing two specific silicon MEMS devices namely, an Absolute Capacitive Pressure sensor and an Infra-Red Sensor. Important issues in design, simulation, process, test and system integration for such devices will be discussed.
Friday, 29th June, 2001, 1430 hrs
Lecture by Dr. Prasad Raje , CEO and Founder, Instantis
"A Silicon Valley Startup Story - An ongoing perspective"
Venue: EE Seminar Hall, IIT Powai, Mumbai (Phone: 5723655)
Activity of AP/ED Chapter of Bombay Section
Abstract:
This is a story about a Silicon Valley startup with a twist. There is no successful or unsuccessful endpoint to report. This is simply a view from the middle - from someone who is there now and going through it. How do companies get started, how are great investors, VCs and employees brought in, how is the product developed, how are customers won, how is value created,what are the challenges being faced? How will the story end? We dont know, time will tell.
Wednesday, 13th June, 2001, 1130 hrs
Lecture by Professor Nirmalendu Chatterjee , Jadavpur University, Kolkata
"Impulse Behaviour of High Voltage Transformer and its Testing Techniques"
Venue: EE Seminar Hall, IIT Powai, Mumbai
Activity of PES/IAS Chapter of Bombay Section
Abstract:
A high voltage transformer is subjected to transient over voltages due to lightning and switching surges. The insulation provided to withstand the power frequency highest system voltage is often found inadequate due to non uniform voltage distribution across the transformer winding specially under lightning impulse. The degree of non uniformity depends on the ratio of equivalent shunt and series capacitance. The search for a suitable design led to the development of interleaved winding. The efficiency of a design can be tested on a model using analogue and digital techniques. The digital simulation of a 31.5 MVA , 132 kV Transformer shows that interleaving can reduce the degree of non uniformity to a large extent in the main winding but the regulating winding suffers from part winding resonance which may lead to break down of insulation. The part winding resonance can be damped to a great extent by the use of graded interleaving technique. The testing technique involves detection of fault under rated impulse voltage and its location. Fault identification can be done by visual investigation of current oscillograms or by digital techniques. Frequency Spectrum Analysis is a reliable tool in fault diagnosis. Use of ANN and Neuro Fuzzy techniques helps in the location of fault. However, a generalised technique in the location of fault in all types of winding is yet to be evolved.
Tuesday, 12th June, 2001, 1500 hrs
Lecture by Dr. Dipak K. Basa, Utkal University, Bhubhaneshwar
"Composition & Electrical Properties of SiN Films"
Venue: EE Conference Room, 1st floor EE Department, IIT Powai, Mumbai
Activity of AP/ED Chapter of Bombay Section
Please call 5723655 for more information
Saturday 24th March 2001
"Year 2001 IEEE Bombay Section Student Paper and Project Contest"
Venue: SPCE, Andheri (West)
Wednesday, 21st March, 2001, 1400 - 1800 hrs
Lecture by Dr. Prakash Apte, TIFR, Mumbai
"Half-day Workshop on Microelectromechanical Systems (MEMS)"
Venue: EE Seminar Hall, IIT Powai, Mumbai
Activity of AP/EDS Bombay Chapter
Contents:
HISTORICAL BACKGROUND
- Silicon Pressure sensors
- Micromachining
- MicroElectroMechanical Systems
MICROFABRICATION AND MICROMACHINING
- Integrated Circuit Processes
- Bulk Micromachining
* Isotropic Etching
* Anisotropic Etching
- Bonding
- High Aspect-Ratio Processes (LIGA)
PHYSICAL MICROSENSORS
- Classification of physical sensors
- Integrated, Intelligent, or Smart sensors
- Sensor Principles and Examples
* Thermal sensors
* Electrical Sensors
* Mechanical Sensors
CHEMICAL AND BIOMEDICAL SENSORS
- Chemical and Biosensors
MICROACTUATORS
- Electromagnetic and Thermal microactuation
- Mechanical design of microactuators
- Microactuator examples
* microvalves
* micropumps
* micromotors
- Microactuator systems : Success Stories
* Ink-Jet printer heads
* Micro-mirror TV Projector (opposite of CCD camera chip)
SURFACE MICROMACHINING
- One or two sacrificial layer processes
- Surface micromachining requirements
- Polysilicon surface micromachining
- Other compatible materials
* Silicon Dioxide
* Silicon Nitride
* Piezoelectric materials
- Surface Micromachined Systems : Success Stories
* Micromotors
* Gear trains
* Mechanisms
PACKAGING AND TESTING TECHNIQUES
- Assembly and Packaging
- Testing
Challenges / Responsibilities:
- Develop proprietary MEMS fabrication processes
- Design processes compatible with device requirements
- Transfer fabrication processes from prototype to volume production
- Maintain baselines for existing processes
- Process troubleshooting
Application Areas:
- All-mechanical miniature devices
- 3-D electromagnetic actuators and sensors
- Photonic devices
- Medical devices e.g. DNA-chip, micro-arrays
1st March, 2001, Thursday, 1430 hrs
Lecture by Mr. Sitaraman Iyer, Carnegie Mellon University
"Modeling a CMOS-MEMS Gyroscope"
Venue: EE Seminar Hall, IIT Powai, Mumbai
Activity of AP/EDS Bombay Chapter
Abstract: In the CMOS-MEMS process a standard CMOS process is used for fabrication of MicroElectroMechanical Systems (MEMS). This talk presents the multi-domain modeling efforts required to simulate a CMOS-MEMS gyroscope. Following a brief introduction to the microgyroscope, elastic and electrostatic models needed to capture non-idealities in the gyroscope will be described. Ongoing work on a SPICE-like simulation methodology based on a hierarchy of design levels (similar to that existing in the digital VLSI world) will be outlined. A synthesis tool aimed at automated layout generation from high-level functional specifications of the gyroscope is also being developed on the basis of the simulation framework. This work is being done in collaboration with other researchers at the Carnegie Mellon MEMS Laboratory.
20th January 2001, Saturday 1630 hrs
Lecture by Dr M V Pitke, Fellow IEEE
"Implementing a Fibre Based Broadband Internet and Multimedia Service"
Venue: ITW-Seminar Hall, SNDT, Juhu
Activity of Communications Society Bombay Chapter

19th January 2001, Friday 1430 hrs
Lecture by Dr. Narain Arora , Simplex Solutions Inc., USA
"Challenges of Modeling High-speed Interconnects in CMOS Technology"
Venue: EE Seminar Hall, IIT Powai, Mumbai
Activity of AP/EDS Bombay Chapter
Narain Arora, Ph.D., is Vice President, Technology at Simplex Solutions, Inc. Prior to joining Simplex in 1996 he held several engineering and management positions within DEC's semiconductor division over a 14-year period. The most recent being consulting engineer and manager of DEC's device and interconnect modeling group. His field of interest is semiconductor process/device design and modeling/characterization including VLSI device/circuit reliability and parasitic (interconnect) modeling and extraction. He has given various invited talks and published over 45 Journal papers and authored a book "MOSFET Modeling for VLSI Circuit Simulation: Theory and Practice", Springer-Verlag, NY 1993.

Abstract: As CMOS technology shrinks to Ultra deep sub-micron geometries (below 0.18um), the propagation delay due to interconnects (wiring) begins to dominate the total chip delay. In fact, parasitic due to interconnects are becoming limiting factors in determining circuit performance. An accurate modeling of the interconnects parasitic effects is thus essential in determining various interconnect related issues such as delay (timing), cross-talk, IR drop, power dissipation, electromigration, etc. This talk will cover different approaches available in modeling the interconnects and what are the challenges the chip designers and CAD vendors are facing to solve the problem.
15th January 2001, Monday 1430 hrs
Lecture by Seshu B. Desu , Professor and Head, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003,
"Recent Developments in High Density Solid-State Memories"
Venue: EE Seminar Hall, IIT Powai, Mumbai.
Activity of AP/ED Bombay Chapter.
Abstract:We discuss the recent advances in oxide ferroelectric thin films and their integration into both high-density DRAMs and non-volatile memories (FRAMs). Emphasis will be placed on integration aspects of these thin films, breakdown mechanisms and limits, leakage currents, electrodes and electrode interfaces, scaling to submicron geometries, and deposition techniques.
10 January 2001, Wednesday
One day Tutorial on "Optical Networks - WDM Routed Networks and Role of Wavelength Conversion"
by Prof. Arun K Somani, Fellow IEEE, Nicholas Professor of ECpE, Iowa State University, USA
Venue: IIT Computer Science Lecture Theatre, IIT, Powai, Mumbai.
Joint Activity of Computer and Communications Chapters of IEEE Bombay Section
For details please contact r.muralidharan@computer.org .. or .. pitke@vsnl.com

"Annual General Body Meeting 2000" ..Notice ..Friday 22nd Dec 2000

Slate given by Nominations Committee

RSVP Letter of acknowledgement

Friday 15th Dec 2000 to Sunday 17th Dec 2000

ACE 2000

Theme... "Software Challenges Ahead"

CANCELLED DUE TO UNFORSEEN CIRCUMSTANCES
28 November 2000 Tuesday 1400 hrs
Lecture by Prof. Alan Oppenheim of MIT, USA
"Issues in DSP"
Venue: Either IRCC Lecture Hall or EE Seminar Hall, IIT Bombay, Powai, Mumbai

8th November 2000 Wednesday 1800 hrs
Lecture by Dr. Saifur Rahman, Professor & Director of Alexandria Research Institute, Alexandria, VA USA. "Demand-side Management and Energy Efficiency"
Venue: MSEB hall of M. S. Electricity Board premises at Bandra (E), Mumbai.
Mr. S. D. Deo, Technical Member of MSEB has kindly agreed to preside over the meeting.
Activity of PES Bombay Chapter
Abstract: This lecture will explore the development of the Demand-side Management (DSM) concept and answer questions like -- what is DSM, why DSM, how DSM can be used for energy and capacity savings, and how transmission and distribution credits can be obtained from DSM. The talk will also examine the financial viability (in terms of customer acceptance) and the future of DSM in the age of electric utility restructuring. Various energy efficiency programs being offered by energy service companies and US electric utilities will be discussed. The value of energy efficiency in dealing with the global climate change issues will be investigated. The present times of electrical power shortages have to be handled diligently & efficiently. Maharashtra Electricity Regulatory Commission has made a start by offering reduced rates during lean periods (Rs.0.50 rebate per unit during 10.00 AM to 6.00 PM for HT consumers.) & enhanced rates during peak hours (Rs.0.30 extra charge for units consumed during 9.00 AM to 12.00 Noon & Rs.0.60 extra per unit during 6.00 PM to 10.00 PM) The DSM has become a wide science with many interesting facets.
20th October 2000 Friday 1700 hrs
Lecture by Tapas Datta, Sr. Design Manager, Intel Bangalore
"Front End Design Methodology for multi-million gate ASICs"
Venue: EE Seminar Hall, IIT Bombay, Powai, Mumbai
Activity of ApEds Bombay Chapter
Abstract: The talk draws from the current experience at Intel, Bangalore of designing such multi-million gate ASICs. It starts with what happens at Project kickoff in defining the ASIC as a part of a System solution for market requirements, how technology selection is done, how chip complexity and chip /board cost is estimated, and how development resources and schedule are estimated. The body of the talk is on the sequential front end steps in designing the ASIC - Architecture, micro-architecture, usage of IP cores, RTL, Design for test, validation, floorplan, synthesis, timing analysis - using examples from real-life multi-million gate ASICs being designed in the industry. The talk also touches on Project management aspects, and waterfall vs spiral model for development. Finally comments are made about what key issues must be driven in order to make a project of this size and complexity achieve first silicon success.
9th October 2000 Monday 1730 hrs
Lecture by Prof P V S Rao, Tata Infotech
"Engineering Approach to Cognition"
Venue: Ramrao Adik Institute of Technology (RAIT), Navi Mumbai.

6th September 2000 Wednesday 1430-1630 hrs
Panel Discussion on "Careers in VLSI in India"
Venue: EE Seminar Hall, IIT Bombay, Powai, Mumbai
Activity of ApEds Bombay Chapter

29th and 30th August 2000 Tuesday and Wednesday 1400 - 1700 hrs
Screening of 1999 International Electron Devices Meeting (IEDM)
Short Course Videos (running time 6 hours) on "Sub-100 nm CMOS"
Venue: EE Seminar Hall, IIT Bombay, Powai, Mumbai 400076
Activity of ApEds Bombay Chapter