The following Lecture Meeting has been organized by the Section.

DAY: THURSDAY
DATE: MARCH 22, 2007
TIME: 4 PM
VENUE: ROOM NO. T-3-7 OF DEPTT. OF ETCE, JADAVPUR UNIVERSITY

1. The fundamentals of GSM – Mr. Debjit Saha, JTE, BSNL, Kolkata

2. Network planning and optimization – Mr. Debasish Ghosh, JTE, BSNL, Kolkata

 

All interested are cordially invited to attend the meeting.

S.K.SANYAL
Chairman
 

ANNUAL SOCIAL PROGRAM

 DAY: SUNDAY

 DATE: JANUARY  28, 2007 

VENUE: HONEY POT, KINNISON JUTE MILL, TITAGURH

Departure from Ramkrishna Mission Institute of Culture, Golpark : 8:30 AM

( Southern Avenue Side Main Gate )

 Departure from Ultadanga, ( Near VSNL Tower ) : 9:00 AM

 Arrival at Titagurh : 10:00 AM

 Departure from Titagurh : 5:00 PM

CHARGE : RS. 200.00 PER PERSON ABOVE 12 YEARS OF AGE 

For further details, please contact

 Mr. Sanjay Kar Chowdhury

Mobile : 98302 02106

sanjay.chowdhury@cesc.co.in

Prof. Kesab Bhattacharya

Mobile: 98300 21794

kesab@ieee.org

LECTURE NOTICE

IEEE CALCUTTA SECTION AND EDS CHAPTER
JOINTLY ORGANISE DISTINGUISHED LECTURE

Miniaturization of Semiconductor Devices
for Integrated Circuits

Hiroshi Iwai
Frontier Collaborative Research Center, Tokyo Institute of Technology
4259, Nagatsuta-cho, Midori-ku, Yokohama, 226-8502, Japan
E-mail: iwai@ep.titech.ac.jp

Among numerous great inventions made in the 20th century, electronics is the most important one. According to a recent survey, “Electronic End Equipment’ has become the base of all human political and economical activities staked a share of the world’s total GDP of about 30,000 billion US dollars. Almost every thing related to human activities, such as power generation, transportation, entertainment, medical care, is now provided and controlled by electronics. Semiconductor, being the key component of the “Electronic End Equipment”, is a strategically important technology for all countries.
The semiconductor electronic circuit development has been accomplished with the downscaling of component size since the replacement of vacuum tubes with transistors 40 years ago. The circuit characteristics have benefited a lot from the downsizing. We are now able to integrate millions of CMOS transistors in the nanoscale in a silicon chip with few centimeters square. The CMOS integrated circuits as well as their core device technology are expected to evolve further for at least a couple of decades and their importance will be further increased in future intelligent society.
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not because of many reasons such as insufficient current drive and huge manufacturing cost. This paper reviews the challenges of nano-CMOS downsizing and manufacturing. We shall focus on the recent progress on the key technologies for the nano-CMOS IC fabrication in the next fifteen yeas. Then, possible limitation for the downscaling of CMOS and post downscaled CMOS technologies are discussed from many aspects.

NOTICE

IEEE CALCUTTA SECTION and IEEE EDS CALCUTTA CHAPTER JOINTLY ORGANISE TECHNICAL TALK BY

DR. BEDABRATA PAIN

CMOS IMAGER TECHNOLOGY R&D LEAD

JET PROPULSION LABORATORY, CALIFORNIA INSTITUTE OF TECHNOLOGY

 480 OAK GROVE DRIVE MS 3000-149

PASEDENA CA91109 USA.

IEEE Lecture Meeting

A Lecture Meeting as detailed below is being organised by IEEE Calcutta Section in collaboration with the Deptt. of ETCE, Jadavpur University.

 

All interested are cordially invited to attend the Lecture Meeting.