Presentation: Clock and Data Recovery Techniques for Optical Communication Systems, Kumar Lakshmikumar, August 19, 2015
Abstract
Clock and Data Recovery (CDR) is a key function in a communication
system. We begin this part of the course with a review of the fundamentals
of CDR in Non-Return-to-Zero (NRZ) serial links. System level metrics like
jitter-tolerance, jitter-transfer and jitter-generation are introduced to
evaluate the performance of a CDR. Several CDR architectures are discussed.
Their advantages and drawbacks specifically for high-speed optical systems
are compared. Many optical systems require a reference-less CDR. Various
techniques to extract frequency from the incoming data are explained in
detail. Linear and bang-bang phase detectors at full-rate are introduced.
Sub-rate structures that ease the speed requirements of the circuits are
also described.
Biography
Kadaba R. (Kumar) Lakshmikumar received his B.E and M.E. degrees in Electrical
Communication Engineering from the Indian Institute of Science, Bangalore,
India, and Ph.D. degree in Electrical Engineering from Carleton University,
Ottawa, Canada. He did pioneering work in the area of modeling mismatch in
MOS devices for his doctoral work. He has held senior engineering and
management positions at Bell Labs, Multilink and Conexant Systems. Currently
he is leading an analog group at Cisco Systems' Silicon Photonics division
in Allentown, PA.
He developed physics-based models to describe the random mismatch in MOS
transistors. The standard deviation of mismatch was shown to be inversely
proportional to the square-root of the channel area. His paper in the
December 1986 issue of the IEEE Journal of Solid-State Circuits is among
the top 20 cited publications of the journal between 1968 and 1992.
Reference
These models are valid even today after the feature size has scaled down
by orders of magnitude through several technology nodes.
Kumar presented a tutorial titled "PLL Design in Nanometer CMOS" at ISSCC
2010. This presentation highlights the benefits and more importantly the
challenges of designing PLLs in Nanometer CMOS processes. The
tutorial
illustrates design techniques for overcoming large variability, low supply
voltage and high leakage.
He has served on the Technical Program Committees of IEEE Custom Integrated
Circuits Conference and IEEE International Solid State Circuits Conference.
Currently he is on the T echnical Program Committees of IEEE Compound
Semiconductor Integrated Circuit Symposium. He is also an associate editor
of the IEEE Journal of Solid-State Circuits. He has several papers and
patents to his credit. He is a Fellow of the IEEE.
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