Presentation by Yorgos Plaskas, Intel Labs, April 23, 2013

• Abstract
  Integration of RF together with baseband and possibly application processors in a System-on-Chip is appealing for cost and form-factor reasons. Conventional radios are generally incompatible with SoC: they require accurate RF models (which prevents quick SoC porting to the next process node), and they might suffer from inverse CMOS scaling due to the lowering supply voltage, inductors getting larger etc. Scaling-friendly radios, on the other hand, introduce fundamentally different ways to encode the information that alleviates these issues. For example, the information can be encoded in the phase of the signal, rather than the amplitude, resulting in improving resolution and performance with CMOS scaling. The circuits now operate in switching mode and can be adequately described with a basic digital MOS model (hence no need for RF models), and certain RF blocks might be possible to implement with digital Auto-Place-and-Route, which would further improve time-to-market. Advanced DSP and digital calibration integrate seamlessly in these systems and can further enhance the performance. The talk will present case studies demonstrating the potential of such scaling-friendly radio concepts. For example, a digital 32nm WiFi transmitter will be presented that is based on high resolution, digitally-controlled delay cells that introduce the modulation. The transmitter includes a switching, inverter-based power amplifier that was designed with no RF models and still closely matched design targets. Presented scaling-friendly radio systems achieve compelling performance already in 32nm CMOS and are expected to further improve with further CMOS scaling, almost on par with digital circuits.
• Biography
  Yorgos Palaskas (S 98, M 02, SM 11) received the Diploma in Electrical and Computer Engineering from the National Technical University of Athens, Greece, in 1996, and the M.S. and Ph.D. degrees, both in Electrical Engineering, from Columbia University, New York, in 1999 and 2002, respectively.
  Since 2003 he has been with Intel Labs, Hillsboro, Oregon, where he is currently an engineering manager. During 2003-2005 he worked on integrated MIMO transceivers and power amplifiers for WiFi. Since 2006 he has been leading research projects on scaling-friendly, SoC compatible, WiFi-WiMAX radios in heavily scaled CMOS processes, and also research on 60GHz radios for multi-Gb/s wireless communications. He has authored and co-authored more than 40 papers at IEEE journals and conferences, 1 book chapter, and has 16 patents issued and several pending.
  He is currently serving on the Technical Program Committee for the IEEE International Solid-State Circuits Conference and the IEEE European Solid-State Circuits Conference.