Presentation by Jan Craninckx, IMEC, Leuven, Belgium May 30, 2013

• Abstract
  This talk discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8-10bit and a few 10's of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of reach of the typically used pipeline architecture. The second part of this paper discusses some specific state- of-the-art designs. The charge-sharing SAR ADC architecture is introduces, which proposes a new signal processing method in the charge domain that removes the often-neglected though requirements for the reference buffer. A high-speed design that combines time-interleaving, pipelining and SAR techniques achieves 10 ENOB and 250MS/s at a figure of merit of 10fJ.
• Biography
  Jan Craninckx obtained his Ms. and Ph.D. degree in microelectronics summa cum laude from the ESAT-MICAS laboratories of the Katholieke Universiteit Leuven in 1992 and 1997, respectively. His Ph.D. work was on the design of low- phase noise CMOS integrated VCOs and synthesizers, where he was a pioneer in RFCMOS design. From 1997 till 2002 he worked with Alcatel Microelectronics (now part of STMicroelectronics) as a senior RF engineer on the integration of RF transceivers for GSM, DECT, Bluetooth and WLAN. Since 2002 he is a principal scientist in the wireless research group in IMEC (Leuven, Belgium) where his research interests are in the design of RF transceivers for software defined radio (SDR) systems. Dr. Craninckx has authored and co- authored more than 60 papers, several book chapters and has published one book in the field of analog and RF IC design. He is the inventor of 10 patents, and is a member of the Technical Program Committee for both the ISSCC and ESSCIRC conferences.