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Ian Rippke - Chair, IEEE Member
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Dr. Ian Rippke is a Senior Applications Engineer and RFIC Specialist
at Agilent Technologies. In this position he has trained
and supported RFIC design engineers throughout the US on
Agilent's GoldenGate simulation tools. For 2 years prior
to Agilent he was the East Coast Applications Engineer with
Xpedion Design Systems, which was acquired by Agilent in 2006.
His background is in RFIC design, specifically SiGe and CMOS
power amplifiers. He holds a BSEE from Lafayette College
and a Ph.D. from Cornell University
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Paul Davis - Vice Chair, IEEE Fellow
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Bio -- TBD
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Roger Minear - Treasurer, IEEE Senior Member
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Roger Minear received B.S. and M.S. degrees from the California
Institute of Technology, and the Ph.D. degree from Stanford University.
He was with Bell Telephone Laboratories, Lucent Technologies, and
Agere Systems from 1970 to 2004. His work involved design and design
management in CMOS and complementary bipolar IC technologies.
Roger served on the ISSCC Technical Program committee from 2000 to 2006.
He is a senior member of IEEE.
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Robert Peruzzi - Secretary, IEEE Senior Member
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Robert Peruzzi received the B.S. degree from Northeastern University
and the M.S. and Ph.D. degrees from Lehigh University. He was with LTX
Corporation in Westwood, MA, then Bell Laboratories, Lucent
Technologies, Agere Systems, LSI and Infineon Technologies in Allentown
PA from 1990 to 2008. His work included ATE, IC Design,
Behavioral Modeling and Mixed-Signal IC Verification. Since
November 2009 he is president of R. Peruzzi Consulting, Inc.
specializing in RF/Analog/Mixed-Signal Behavioral Modeling and
Verification.
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Richard Booth - Webmaster,
IEEE Senior Member
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Richard Booth received the B.S. degree from the University of Maryland,
and the M.S. and Ph.D. degrees from Lehigh University.
He was with IMEC, vzw, Leuven, Belgium, from 1989 to 1992 working on
process and device simulation and optimization. From 1992 to 2006, he
was with Bell Laboratories/AT&T, Lucent Technologies,
and Agere Systems, Allentown, PA, working on compact-modeling,
device testing, and PLL design.
He is currently at Lattice Semiconductor, Bethlehem, PA, working on
design of PLL's, 6G SerDes, differential I/O buffer and other
analog, digital and mixed-signal circuits. He supports the open-source
tool decida for procedural simulation, device modeling, and data
visualization.
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