Fundamentals of Digital Logic Design with VHDL (Hardcover)

ISBN-13: 9780981619446,

ISBN-10: 0981619444,

http://www.amazon.com/dp/0981619444


Readership: Comprehensive textbook is for courses in Digital Design, Digital Logic, Digital Electronics, VLSI Design, ASIC Design, and VHDL; in addition, the book is a great reference for practicing engineers, scientists and professionals who may be involved with the design of digital systems, VLSI circuits, printed circuit boards, multi-chip modules, and computer hardware circuits and systems.


About the Author: Michael Hassan earned B.S. in Electrical Engineering, M.S. in Electronics Engineering; and M.S. and Ph.D. in Electrical and Computer Engineering from WSU, Michigan, USA. He is a senior member of IEEE, the Institute of Electrical and Electronics Engineers, a member of Sigma Xi, the Scientific Research Society, a member of Tau Beta Pi, the Engineering Honor Society, and a member of Eta Kappa Nu, the Electrical Engineering Honor Society. Professor Hassan taught Digital Logic Design courses in a number of universities for more than twenty years, and published many scientific papers and textbooks in the field of Electrical, Computer, and Systems Engineering. He is also an inventor with a significant number of inventions and intellectual properties. His teaching, research, and consulting interests include digital systems theory and design, analog and digital integrated circuit design, microcomputer systems, microelectronics and VLSI design, reconfigurable computing, image processing and vision systems, communication systems and networks, electric vehicles, and alternative energy systems. He is currently professor and research scientist offering engineering consulting and on-site courses in electrical, electronics, computer, aerospace, and systems engineering, a list of which can be found at http:/innovatellc.org/. Dr. Hassan is a licensed professional engineer and the recipient of the IEEE Outstanding Engineering Educator Award.

Contents of the book:

Chapter 1: Number Systems
1.1 Introduction
1.2 Number Systems
1.3 Conversion of Bases
1.4 Binary Arithmetic
1.4.1 Binary Addition
1.4.2 Complements
1.4.3 Binary Subtraction
1.4.3.1 Direct Binary Subtraction
1.4.3.2 Binary Subtraction Using the 1's Complement Method
1.4.3.3 Binary Subtraction Using the 2's Complement Method
1.4.4 Binary Multiplication
1.4.5 Binary Division
1.5 Signed and Unsigned Numbers
1.6 Floating-Point Binary Numbers
1.7 Binary Codes
1.7.1 Weighted Codes
1.7.2 Non-weighted Codes
1.7.3 Error-Detecting Codes
1.7.4 Error-Correcting Codes
1.7.5 Alphanumeric Codes
1.8 Introduction to VHDL
1.8.1 VHDL Levels of Abstraction
1.8.2 Using VHDL for Design Synthesis
1.8.3 Design Flow
1.8.4 Modularity and Hierarchy
1.8.5 VHDL Keywords
1.8.6 Naming Convention
1.8.7 Signal Declarations
1.8.8 BIT and BIT_VECTOR Types
1.8.9 STD_LOGIC and STD_LOGIC_VECTOR Types
1.8.10 STD_ULOGIC and STD_ULOGIC_VECTOR Types
1.8.11 SIGNED and UNSIGNED Types
1.8.12 INTEGER Types
1.8.13 BOOLEAN Types
1.8.14 Enumeration Types
1.8.15 Physical Types
1.8.16 Composite Types
1.8.17 Subtypes
1.8.18 Aliases
1.8.19 Type Conversion
1.8.20 Constant Declarations
1.8.21 Variable Declarations
1.8.22 File Declarations
1.8.23 Operators
Problems

Chapter 2: Logic Gates and Boolean Algebra
2.1 Introduction
2.2 Logic Gates
2.2.1 Inverter or NOT Operation
2.2.2 AND Operation
2.2.3 OR Operation
2.2.4 NAND Operation
2.2.5 NOR Operation
2.2.6 Exclusive OR Operation
2.2.7 Exclusive NOR Operation
2.3 Boolean Functions
2.3.1 Combinational Network Synthesis
2.3.2 Combinational Network Analysis
2.3.3 Constructing the Truth Table
2.3.4 The Complement of a Function
2.4 Laws and Theorems of Boolean Algebra
2.4.1 Principle of Duality
2.4.2 Operations with 0 and 1
2.4.3 Idempotent Laws
2.4.4 Involution Law
2.4.5 Laws of Complementarity
2.4.6 Commutative Laws
2.4.7 Associative Laws
2.4.8 Distributive Laws
2.4.9 Simplification Theorems
2.4.10 De Morgan's Theorems
2.4.11 Theorems for Multiplying Out and Factoring
2.5 Standard and Canonical Forms
2.6 Incompletely Specified Functions
2.7 Logic Gates Using VHDL
2.7.1 ENTITY Declaration
2.7.2 ARCHITECTURE Declaration
2.7.3 COMPONENT and PACKAGE Declaration
2.7.4 Concurrent Assignment Statements
2.7.5 Sequential Assignment Statements
2.7.6 Buffer
2.7.7 Inverter
2.7.8 AND Gate
2.7.9 NAND Gate
2.7.10 OR Gate
2.7.11 NOR Gate
2.7.12 Exclusive OR Gate
2.7.13 Exclusive NOR Gate
2.7.14 Examples on Design Hierarchy
2.8 Design with Logic Gates
Problems

Chapter 3: Analysis and Design of Combinational Networks
3.1 Introduction
3.2 Irredundant and Minimal Functions
3.3 Karnaugh Maps
3.3.1 Two-Variable Map
3.3.2 Three-Variable Map
3.3.3 Four-Variable Map
3.3.4 Five-Variable Map
3.3.5 Six-Variable Map
3.3.6 Properties of Minimal Functions
3.3.7 Incompletely Specified Functions
3.3.8 Complement of a Function
3.3.9 Canonical and Standard Forms from the Map
3.3.10 Two-level Implementations
3.3.11 Plotting Functions on the Map
3.4 Design of Multiple-Output Combinational Networks
3.5 Variable-Dependent Functions & Map-Entered Variables
3.6 Propagation Delay and Timing Hazards
3.7 Quine-McCluskey Method
3.7.1 Prime Implicants Chart
3.7.2 Incompletely Specified Functions
3.7.3 Petrick's Method
3.8 Design of Combinational Networks Using VHDL
3.8.1 BCD To 7-Segmnet Decoder
3.9 Timing Verification
Problems

Chapter 4: Combinational Network Design With Standard Modules
4.1 Introduction
4.2 Decoders
4.2.1 Decoder Expansion
4.2.2 Implementing Switching Functions with Decoders
4.2.3 Code Converters
4.3 Encoders
4.4 Multiplexers
4.4.1 Multiplexer Expansion
4.4.2 Implementing Switching Functions with Multiplexers
4.5 Demultiplexers
4.6 Read-Only Memory (ROM)
4.6.1 Implementing Switching Functions with ROMs
4.7 Programmable Logic Array
4.8 Programmable Array Logic
4.9 Complex Programmable Logic Device
4.10 Field Programmable Gate Array (FPGA)
4.11 Design of Standard Modules Using VHDL
4.11.1 Concurrent and Sequential VHDL Statements
4.11.2 Decoders
4.11.3 Encoders
4.11.4 Code Conversion
4.11.5 Multiplexers
4.11.6 Demultiplexers
Problems

Chapter 5: Arithmetic Combinational Network Design
5.1 Introduction
5.2 Binary Adders for Positive Integers
5.2.1 Carry-Ripple Adder
5.2.2 Carry-Lookahead Adder
5.2.3 Binary Subtracters
5.3 Magnitude Comparators
5.4 Binary Multiplier
5.5 Arithmetic and Logic Unit
5.6 Design of Arithmetic Combinational Networks Using VHDL
5.6.1 Half-Adder
5.6.2 Full-Adder
5.6.3 N-Bit Adder
5.6.4 Binary Subtractors
5.6.5 Magnitude Comparators
5.6.6 Binary Multipliers
5.6.7 Arithmetic and Logical Unit (ALU)
Problems

Chapter 6: Flip-Flops
6.1 Introduction
6.2 Representations of Sequential Networks
6.3 Memory Elements
6.4 The SR Flip-Flop
6.5 The Clocked SR Flip-Flop
6.6 The JK Flip-Flop
6.7 The T-Type Flip-Flop
6.8 The D-Type Flip-Flop
6.9 Characteristic Equations
6.10 Tri-state Logic
6.11 Modular Latches and Flip-Flops
6.12 Flip-Flops Design Using VHDL
6.12.1 D-Type Latch
6.12.2 D-Type Flip-Flop
6.12.3 JK Flip-Flop
6.12.4 T-Type Flip-Flop
Problems

Chapter 7: Digital Counters and Registers
7.1 Introduction
7.2 Digital Counters
7.3 Ripple (Asynchronous) Counters
7.3.1 Binary Ripple Down-Counter
7.3.2 Binary Ripple Up-Down Counter
7.3.3 Other Ripple Counters
7.4 Synchronous Counters
7.4.1 Design of Synchronous Counter Using D Flip-Flops
7.4.2 Design of Synchronous Counter Using T Flip-Flops
7.4.3 Design of Synchronous Counter Using JK Flip-Flops
7.4.4 Design of Synchronous Counter Using SR Flip-Flops
7.5 Synchronous BCD Counter
7.6 Synchronous Up-Down Counter
7.7 Synchronous Binary Counter with Parallel Load
7.8 Code Converters
7.9 Modular Counters
7.10 Registers
7.10.1 Parallel-in/Parallel-out Shift Register
7.10.2 Serial-In/Serial-Out Shift Register
7.10.3 Serial-In/Parallel-Out Shift Register
7.10.4 Parallel-In/Serial-Out Shift Register
7.10.5 Bidirectional Shift Registers
7.10.6 Universal Shift Registers
7.10.7 Ring Counter (Cyclic or Circular Shift Register)
7.10.8 Johnson Counter (Twisted Ring Counter)
7.11 Modular Registers
7.12 Design of Counters and Registers Using VHDL
7.12.1 Synchronous Counters with Common Clear
7.12.2 Synchronous Counters with Parallel Load
7.12.3 Synchronous Counters with Parallel Load Using INTEGER
7.12.4 Counters with Parallel Load and Asy. Resets/Presets
7.12.5 Counters with Parallel Load, Asy. Resets and Presets
7.12.6 Counters with Parallel Load and Product-Term Resets
7.12.7 Counters with Tri-State Outputs
7.12.8 Synchronous Down-Counter
7.12.9 RTL Counter Design
7.12.10 Registers
7.12.11 Unidirectional Shift Registers
7.12.12 Bidirectional Shift Registers
Problems

Chapter 8: Analysis of Synchronous Sequential Networks
8.1 Introduction
8.2 Models for Synchronous Sequential Networks
8.2.1 Mealy Model
8.2.2 Moore Model
8.2.3 Medvedev Model
8.2.4 Mixed Mealy-Moore Model
8.3 Analysis of Sequential Networks Using State Graphs or Tables
8.4 Analysis of Sequential Networks by Signal Tracing
8.5 Analysis of Sequential Networks by Deriving the State Graph
8.6 Analysis of Sequential Networks Using VHDL
8.6.1 One-Process FSM Code
8.6.2 Two-Process FSM Code
Problems

Chapter 9: Design of Synchronous Sequential Networks
"Derivation of State Graphs"
9.1 Introduction
9.2 Guidelines for Derivation of State Graphs
9.3 Mealy Sequential Network for a Sequence Detector
9.4 Moore Sequential Network for a Sequence Detector
9.5 Design of a Complex Sequence Detector
9.6 Design of a Two-Input One-Output Sequential Network
9.7 Design of a Two-Input Two-Output Sequential Network
9.8 Design of a Serial Data Code Converter
9.9 Design Examples
9.10 Design Examples with VHDL
Problems

Chapter 10: Design of Synchronous Sequential Networks
"Reduction of State Tables"
10.1 Introduction
10.2 Redundant and Equivalent States
10.3 Reduction of State Tables by Inspection
10.4 Reduction of State Table Using the Merger Graph
10.5 Reduction of State Table Using the Implication Table
10.6 Reduction of State Tables Using the Partitioning Method
10.7 Equivalent Finite State Machines
10.8 Design Examples
10.9 Design Examples with VHDL
Problems

Chapter 11: Design of Synchronous Sequential Networks
"State Assignment"
11.1 Introduction
11.2 Distinct State Assignments
11.3 State Assignment Strategies
11.4 State Assignment Guidelines
11.5 State Assignment Using Partitions
11.5.1 Algebraic Properties of Partitions
11.5.2 Useful Partitions
11.6 Design Examples With VHDL
Problems

Chapter 12: Design of Synchronous Sequential Networks
"Implementation"
12.1 Introduction
12.2 Hardware Implementation Procedure
12.3 Design of Sequential Networks Using Logic Gates
12.4 Design of Sequential Networks Using ROMs
12.5 Design of Sequential Networks Using PLAs
12.6 Design of Sequential Networks Using PALs
12.7 Other Programmable Logic Devices
12.8 Design Examples
12.9 Design Examples With VHDL
Problems

Chapter 13: Digital System Design Using ASM Charts
13.1 Introduction
13.2 Algorithmic State Machine Charts
13.3 Conversions of ASM Charts
13.4 Equivalent ASM Charts
13.5 The Design Process
13.6 Design of Parallel Multiplier
13.6.1 Datapath Section
13.6.2 Control-Logic Section
13.6.3 Control-Logic Section Design With Flip-Flops and Logic Gates
13.6.4 Control-Logic Section Design With Flip-Flops and Decoder
13.6.5 Control-Logic Section Design With Flip-Flops and Multiplexers
13.6.6 Control-Logic Section Design With One Flip-Flop Per State
13.7 Design Examples With VHDL
13.8 Techniques and Heuristics for Design Reliability
13.8.1 Documentation
13.8.2 Modularity
13.8.3 Clock Synchronization
13.8.4 Asynchronous Inputs
13.8.5 Interface Compatibility
13.8.6 Fan-In and Fan-Out
13.8.7 Noise on Power Lines
13.8.8 Signal Integrity
13.8.9 Impedance Matching
13.8.10 Flip-Flops Initialization
13.8.11 Electromagnetic Interface (EMI)
Problems

Chapter 14: Asynchronous Sequential Networks: Analysis and Design
14.1 Introduction
14.2 Fundamental-Mode Networks
14.3 Pulse-Mode Networks
14.4 Analysis of Pulse-Mode Networks
14.5 Design of Pulse-Mode Networks
14.6 Analysis of Fundamental-Mode Networks
14.7 Design of Fundamental-Mode Networks
14.8 Races and Cycles
14.9 Design Examples With VHDL
Problems

Appendix I: Using Quartus II CAD Software
Appendix II: Reserved VHDL Words
References
Index