As CMOS scales into nanometer dimensions, IC designs are more and more interconnect-dominated (ITRS?3). The resulting design closure has been a central problem for electronic design automation, as seen by enormous efforts from both academia and industry. Meanwhile, as CMOS scaling continues, power is becoming a key design limiter. Voltage scaling with multiple supply and threshold voltages is one of the most effective ways to reduce power, but it may perturbate physical layout and timing, thus shall be addressed during the design closure as well. To reduce the turn around time and improve performance/yield, predictive modeling shall also be developed. In this talk, I will discuss several key issues related with nanometer physical design closure, focusing on performance, power, and predictability (3P). The results on the performance-driven design closure will be presented under an interconnectcentric paradigm which emphasizes early interconnect estimation and planning. I will also present some results on multiple Vdd/Vth for low power optimization. Although tremendous efforts have been put, there is still significant gap between what tools can provide today and what the optimal solution is. Such gap seems to increase with ever-growing design complexities and technology challenges (e.g., leakage, noise, uncertainty). I will address future research directions before concluding the talk.