Different from most engineering disciplines, in IC design we do not usually do "full" prototyping. We may try out a few parts of a design on test chips but we do not do full-scale prototyping as would happen -for example- for a car. We rely completely on "models" of the technology to help us predict and assure the performance of our chips. As we have crossed from 90 to 65 and now to 45nm, these models are starting to break down. We have had to add vast amounts of complexity to the fabrication process in order to keep up with scaling. In fact, performance improvement has come more from innovation (OPC/RET, Cu, SOI, Stress) than from straight feature size reduction. This complexity exhibits itself most blatantly in the drastic increase in the number of design rules used to define the technology. We are seeing 10x increases in the number of rules going from 250 to 45nm. So what is needed is better models, and better penetration of these models into the CAD flow. I posit that DFM thus far has been solely about putting manufacturing awareness in design, and that this awareness is only felt at the very lowest levels of typical digital design (layout and schematic). We need manufacturing awareness to move up the stack to the micro-architecture level, in order to best leverage the limited degrees of freedom available for circuit adaptation.