A decade ago, physical synthesis emerged as a design aid to address the problem of optimization after cell placement caused by increasingly high wire delays. Early physical synthesis tools were fairly simplistic scripts wrapped around traditional placement and logic synthesis optimizations. Advances and technology have put increasing pressure on physical synthesis tools not only to perform timing takedown with increasingly aggressive frequences but also to manage many additional design constraints like power management, routability, and variability. Trying to solve all aspects of physical implementation simultaneously creates massive complexity for both the tool and the designer.

This talk overviews the basics of physical synthesis, from placement to buffering to gate sizings and explains fundamentally how a physical synthesis flow weaves together its components to perform timing closure. It explains how the complexity of physical synthesis and corresponding designs have mushroomed to create design problems that are not just bad, but sometimes downright ugly.