The continuous increase in size, complexity, and heterogeneity of embedded system design has introduced new challenges in their modeling and implementation. Multi-Processor System-on-Chip (MPSoC) design requires high speed models for early verification and performance evaluation. As a result, electronic system level (ESL) modeling has moved up in abstraction from cycle accurate RTL to timed and untimed transaction-level models (TLMs). However, the open question is how to get from a high level system description to a hardware/software implementation? The goal of this tutorial is to answer such questions and to provide system designers and managers with new insight into ESL modeling concepts and synthesis techniques for MPSoCs.
In this tutorial, we will cover the key concepts and state of the art tools for MPSoC design. We will discuss TLM semantics for automatic model generation, methods for automatic design space exploration, and hardware/software synthesis. This tutorial is targeted towards embedded software and hardware developers, engineers who use or are interested in using ESL design tools, managers of system designers, and verification engineers.