In nanometer technologies, local interconnects are believed to cause major impact on timing and power in VLSI circuits. Just how large is the impact? This talk answers the question with results from an extensive study carried out to assess the same in a quantitative manner on a real high performance design. The study shows that for RTL-to-layout synthesized (RLS) blocks, in a 45 nm technology microprocessor core, local interconnects contribute nearly 1/3rd each to the timing on the worst internal paths and to the dynamic power dissipation. This points to the severity of impact due to the local interconnects, which is likely to worsen in future. It also implies that algorithms/approaches underlying existing synthesis/physical design tools/methodologies have had limited success in mitigating the same.