Rupesh S. Shelar received Ph.D. in Electrical Engineering from the University of Minnesota, Minneapolis in 2004. He is currently a staff engineer
at Intel Corporation, where he has contributed to Core i5/i7 and Atom microprocessor designs in 45/32/22 nm technologies in the areas of clocking
and interconnect impact analysis. He is a co-author of a book "Routing Congestion in VLSI Circuits: Estimation and Optimization," published by Springer in 2007.