Best practices for analog layout in advanced process nodes
Successful analog design in advanced process nodes requires understanding newly modeled layout effects including length of diffusion (LOD) and well proximity effect (WPE). In older processes these effects were either unknown or not modeled. Proper understanding of LOD and WPE will result in improved analog circuit performance. The talk with describe these new effects and present a number of real examples of WPE and LOD layout problems and fixes.