Over recent years the EDA community has embraced Electronic System Level (ESL) design flow, SystemC, Transaction Level Modeling (TLM) and High Level Synthesis (HLS). Today all major EDA vendors provide the tools needed for an ESL design-flow. With the tools available design teams need to develop a flow that provides early return on investment, creates a foundation for the next generation of products and do this with minimum disruption of the existing designs and design-flow. This presentation will explore the most common ESL use-cases and their relation to traditional SoC design flow. An example ESL design-flow identifies the opportunities and challenges as a team’s traditional design-flow evolves to an ESL flow that includes architecture, hardware, design-verification and software. The common ESL use-cases include early architectural exploration, performance modeling, virtual system prototypes, shared functional verification, and high level synthesis.