The gate-level placement has been around for several decades and is considered a core traditional problem in electronic design automation. Its classic and modular formulation has led to the perception that placement is no longer a particularly interesting or hot topic to work on. Nothing could be further from the truth: placement is at the heart of design quality in terms of timing closure, routability, area, power and most importantly, time-to-market. This session describes many opportunities for research in placement for the next ten years and makes the case that more investment in this fundamental technology would benefit the design community.