As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), the IC manufacturability challenges are exacerbated, due to double/multiple patterning and other emerging lithography technologies. Meanwhile, the vertical scaling with 3D-IC integration using through-silicon-vias (TSVs) has gained tremendous momentum and initial industry adoption, which can further extend the Moore’s Law even the feature size scaling stops ultimately. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for reliable 3D IC integration. This talk will first show how the nanolithography envelope is being pushed with novel design/process integration for multiple patterning lithography as well as other emerging technologies. In 3D-IC, TSV induced thermal mechanical stress not only results in systematic performance variations, but also leads to mechanical and electrical reliability concerns. Cross-layer modeling and physical design techniques will be discussed to achieve future reliable integrated circuits and system integration.