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 Meetings
Past Events:
December NA, 2007
November NA, 2007
October 25, 2007
September 12, 2007
September 26-28, 2007
August 23, 2007
July 26, 2007
June 21, 2007
May 24, 2007
April 26, 2007
March 22, 2007
Febuary 22, 2007
January 7, 2007
Back to Past Events
| Date: |
October 25, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Nanoimprinting |
| Description: |
The drive to manufacture semiconductor devices with ever smaller features has inspired amazing
improvements in imaging materials science and technology for about 3 decades. Billions of dollars
have been spent in efforts to devise methods and materials that enable the printing of ever smaller
transistors. The lithographic process that has been used to generate these "nano-structures" is
becoming extremely expensive and the cost of that process threatens the economics of the semiconductor
manufacturing industry. Imprint lithography, a much lower cost, high resolution patterning technology
is emerging as a potential adjunct to photolithography. Imprint lithography loosely defines a set
of techniques that include several forms of embossing; stamping and molding that show great promise
as low cost methods for producing nanostructures. These techniques take many different forms, each
of which has its own special applicability. The technique we call Step and Flash Imprint Lithography
(S-FIL) is designed to allow the fabrication of high resolution, high aspect ratio images that can be
aligned with precision. The process accurately replicates very small arbitrary shapes. Structures
smaller than 5 nanometers in width have been faithfully reproduced. The state of high resolution
imaging processes for production of devices with nanoscale features will be presented with emphasis
on Step and Flash Imprint Lithography Process.
|
| Speaker: |
Professor Grant Wilson |
| Speaker Bio: |
Dr. Willson joined the faculties of the Departments of Chemical Engineering and
Chemistry at the University of Texas at Austin in 1993. He received his BS and Ph.D. in Organic Chemistry from the University of California at Berkeley and an MS degree in Organic Chemistry from San Diego State University. He came to the University of Texas from his position as an IBM Fellow and Manager of the Polymer Science and Technology area at the IBM Almaden Research Center in San Jose, California. He joined IBM after serving on the faculties of California State University, Long Beach and the University of California, San Diego. Dr. Willson is a member of the ACS, APS, SPIE, SPE, AAAS, ASEE, and Sigma Xi and is a member of the National Academy of Engineering. He currently supervises two visiting scientists, 15 graduate students, and 6 undergraduate students. He serves on the editorial boards of several journals in polymer chemistry and materials science, serves as associate editor of ACS NANO and is co-author of over 400 journal publications. He is editor and author of several books and co-inventor on more than 50 issued patents. Dr. Willson's research can be characterized as the design and synthesis of functional organic materials with emphasis on materials for microelectronics. These include monomeric and polymeric liquid crystalline materials, polymeric non-linear optical materials, novel photoresist materials, etc. This work is supported by grants from both government and industry. His work in photoresist research has been honored by the Arthur Doolittle Award, the Chemistry of Materials Award, the Carothers Award, Applied Polymer Science Award and the Heroes in Chemistry Award from the American Chemical Society, the Alexander von Humboldt Senior Scientist Award from the Federal Republic of Germany, the ACS Award for Cooperative Research in Polymer Science and Engineering, the SRC Technical Excellence Award, the SRC Aristotle Award, the Malcolm E. Pruitt Award and the Frits Zernike Award from SPIE. He has been appointed Fellow of the PMSE Division of ACS and of SPIE. He is the recipient of the 1999 National Academy of Sciences Award for Chemistry in Service to Society. |
|
| Date: |
September 12, 2007 |
| Time: |
6:30PM - 9:30PM |
| Location: |
Dell, Inc.
Technology Briefing Center
Parmer South 3
701 E. Parmer Lane.
Austin, TX 78753
|
| Topic: |
The Needs and Challenges of the $100 Laptop |
|
| Date: |
August 23, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
The impact of nanotechnology on the current semiconductor microelectronic industry |
| Description: |
Nanotechnology is a new scientific field evolving from material-specific peculiarities of present
elements when their sizes become nanometric (one nanometer corresponds to the millionth part of one millimeter)
. The commercialization of nanotechnology involves the creation and utilization of new functional materials,
devices and systems based on the novel functions and properties of nanometric-size elements. In order to
succeed in exploiting nanotechnology in the semiconductor industry, new techniques must be developed to
organize, characterize and manipulate individual nanoscale elements. Furthermore, insights into
self-organization principles of these nanoelements are necessary. The immediate commercial impact will
result from implementation of nanoscale architectures with new microscopic and macroscopic functions. In
particular, many believe that nanotechnology will eventually catalyze the unification of processes of the
living (biotechnology and genetic engineering) with the non-living worlds (electronics and materials
processing). My presentation will focus on three most important contributions of nanotechnology to the
future semiconductor industry: 1. Top down nanostructures. The top down strategy is based on decreasing
structural dimensions as is desired in microelectronics. In order to extend Moore’s Law to the nanometric
world, we need to transit from microelectronics to nanoelectronics. The transition requires, in addition to
the extension of the lithographic limits, a new understanding of the laws of physics as we move from the
continuum to quantum. New techniques will be employed to create sub-100-nanometer scale structures
(i.e. writing with light, particle beams and ink.) 2. Bottom up nanostructures. The bottom up strategy is
based on achieving larger systems from very small units through self-organization. The principles of
self-organization are based on the specific properties of organic/inorganic boundary surfaces and the
selective chemical/physical coupling of molecular systems to properly prepared surfaces. These structures
are required for full convergence of nanotechnology and biotechnology that eventually will combine the
advantages of top down structures and bottom up structures. 3. Nanotechnology and biotechnology convergence.
Biotechnology and nanotechnology are merging. These extremely potent technologies will drive technological
innovation and commercialization during the 21st century. Biotechnology was able recently to solve the
human genome puzzle and to identify the 23 separate pairs of chromosomes. These chromosomes that are
essentially the fabric of life are each made of a pair of very long DNA molecules. It is remarkable that
the DNA molecules are themselves a nanometric particle. On one hand, nanotechnology teaches us how to
exploit novel properties of materials when they become nanoscopic. We are even able to build working devices
on a nanometric scale and interface these nanometric devices on a molecular level. On the other hand, these
devices can be built with features so small that they can interact with cells, biomolecules and DNA. This is
why nanotechnology and biotechnology are converging. Ultimately, biological structures can serve as
components for mechanical and electrical nanosystems and vice versa. It is my belief that if the
electronics must eventually shrink down to the nanometer scale, the only answer will be the utilization of
biological molecules, with their ability to self-assemble with different electronic magnetic and optical
materials in whatever patterns one desires. |
| Speaker: |
Dr. Zvi Yaniv
Applied Nanotech, Inc.
|
| Speaker Bio: |
Dr. Zvi Yaniv is the President and Chief Operating Officer of Nano-Proprietary, Inc.
(NPI, www.nano-proprietary.com) and the President and Chief Executive Officer of Applied Nanotech, Inc.
in Austin, TX, guiding the company to become a pioneer in nanotechnology in general and a leader in the
display industry utilizing electron field emission from carbon films/carbon nanotubes, in particular.
Dr. Yaniv is an authority in electro-optics, liquid crystal technology, amorphous semiconductors, technology
commercialization and business management. He has published over 200 articles, holds more than 150 patents,
and has extensive contacts in the U.S., Europe, Israel and the Far East. Dr. Zvi Yaniv was a founder
of Kent Display Systems in Kent, Ohio, the "no-power" reflective LCD Company and of OIS Optical Imaging
Systems, Inc. in Novi, Michigan. As President and CEO of OIS, Inc., he led the company during its years
of development and initial commercialization of advanced active matrix liquid crystal displays and amorphous
silicon image sensors. While at OIS, Dr. Yaniv was one of the founders of Unipac (now AU Optronics),
currently one of the premier display companies in Taiwan. Earlier, Dr. Yaniv held ranking positions
with the Practical Engineering College, Beer-Sheva; National Institute for Technical Training, Tel-Aviv;
and Ben-Gurion University of the Negev. In 1999, Dr. Yaniv introduced a new expression of kinetic art
(Digital Windows, www.digitalwindows.net), allowing static two- or three- dimensional artworks to become
dynamic and interactive. Dr. Yaniv holds a B.Sc. in physics/mathematics and a M.Sc. in electro-optics
with distinction from the Hebrew University of Jerusalem, and earned a M.Sc. and a Ph.D. in physics at
Kent State University. He has received awards from both universities and the Scientific Research Society.
Dr. Yaniv is a member of the Board of Directors of NPI, the Nanoparticles Applications Center of Texas State
University and the Society for Information Display (SID). In May 1989, Dr. Yaniv was elected Fellow of the
Society for Information Display for "his innovation and leadership in the development of large area high
performance active matrix LCDs and scanners." As a member of the SID, Dr. Yaniv founded two chapters of
the Americas Region: the Metropolitan Detroit and the Texas Chapters and served as director of these chapters
for more than ten years. In March 2000, Dr. Yaniv was nominated and he accepted the honorific title of
Senior Research Fellow of the IC2 Institute of the University of Texas. In January 2001 Dr. Yaniv founded
the Nanomaterials Applications Center, now affiliated with Texas State University. In December 2003 Dr.
Yaniv was nominated and accepted to become a strategic advisor to Governor Nobuyoshi Sumita of Shimane
Prefecture in Japan in the field of job creation utilizing the advances in nanotechnology. |
|
| Date: |
July 26, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Modeling and simulation issues and approaches for ultimate CMOS and beyond. |
| Description: |
The International Technology Roadmap for Semiconductors calls for CMOS devices with physical gate lengths
of 18 nm by the end of this decade, and 6 nm by the end of the next, while of course maintaining acceptable
operating characteristics including drive currents and on-off ratios. To achieve these goals, so-called
“non-classical CMOS” devices are being considered with strain and alternative device geometries, channel
crystal orientations, and channel and gate stack materials. Modeling and simulation can provide a powerful
tool to help guide us through the maze of possibilities offered by non-classical CMOS toward the most promising
solutions. However, the continued scaling and the consideration of non-classical CMOS also pose challenges
to modeling and simulation itself. In this presentation, I will discuss these challenges, describe simulation
tools that have been developed or are in development by myself and colleagues within the Microelectronics
Research Center at UT-Austin to help address theses challenges, and present results of these simulation that
illustrate the essential physics of operation of CMOS as we progress toward the end of the current
semiconductor roadmap. Of course, power scaling subject to minimum voltages defined by the fundamental
physical process of thermionic emission is the issue that may define the end of the roadmap for CMOS.
This limit is now the driving force for looking “beyond CMOS.” And while efforts in this area by us and
others are largely in their infancy, I will address this issue as well as time allows. |
| Speaker: |
Prof. Leonard Franklin Register
University of Texas at Austin |
| Speaker Bio: |
Leonard Franklin Register is an Associate Professor of Electrical and Computer Engineering
and the University of Texas at Austin, a member of the Microelectronics Research Center and recipient of the
Temple Foundation Endowed Faculty Fellowship #4. Dr. Register has B.S. degrees both in Electrical Engineering
and in Physics and a Ph.D. in Electrical Engineering earned under the supervision of Prof. Michael Littlejohn from
North Carolina State University. After graduation, he joined the research faculty at the Beckman Institute at the
University of Illinois at Urbana-Champaign as a post doctoral student under the supervision of Prof. Karl Hess,
later becoming a research scientist. He joined the faculty of The University of Texas at Austin in 2000.
Dr. Register is a device theorist with published research in diverse fields including semiclassical and quantum transport,
scattering theory, CMOS performance and reliability, single electronics and lasers. His current research interests
include physically accurate yet practical modeling of strain and overt quantum effects on charge carrier transport in
non-classical CMOS, and use of alternative mechanisms of switching and perhaps alternative state variables such as
spin to provide, e.g., lower power computation than possible with CMOS. |
|
| Date: |
June 21, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Chemical and Biological Sensors |
| Description: |
|
| Speaker: |
Dr. Daniel Fine
University of Texas at Austin |
|
| Date: |
May 24, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
MRAM overview |
| Description: |
|
| Speaker: |
Dr. Chitra K Subramanian
Freescale Semiconductors |
| Speaker Bio: |
Chitra Subramanian received her Ph.D. degree in Electrical Engineering from Purdue University in 1993.
She joined Motorola's Advanced Products Research and Development Lab in 1993 as a device engineer and worked
in 0.25um and 0.18um SRAM development. From 1997 to 2000 she worked on 0.18um
embedded DRAM development first as a device engineer in trench capacitor embedded DRAM development and then
as a circuit designer on a stacked capacitor embedded DRAM for wireless and printer applications. Since 2000
she has been working on MRAM circuit design and was the project leader for the first ever commercially a
vailable 4Mb MRAM product design. Chitra has co-authored 21 publications and has 28 issued patents. |
| Slides: |
Chitra Subramanian's Slides (pdf) |
|
| Date: |
April 26, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Optical Interconnects: A Viable Solution for Interconnection Beyond 10 Gbit/sec |
| Description: |
The speed and complexity of integrated circuits are increasing rapidly as integrated circuit technology advances from very-large-scale integrated (VLSI) circuits to
ultra-large-scale integrated (ULSI) circuits. As the number of devices per chip, the number of chips per board, the modulation speed, and the degree of integration continue
to increase, electrical interconnects are facing their fundamental bottlenecks, such as speed, packaging, fan-out, and power dissipation. In the quest for high-density packaging
of electronic circuits, the construction of multichip modules (MCM), which decrease the surface area by removing package walls between chips, improved signal integrity by shortening
interconnection distances and removing impedance problems and capacitances. The employment of copper and materials with lower dielectric constant materials can release the bottleneck
in a chip level for the next several years. The International Technology Roadmap for Semiconductors (ITRS) expects that on-chip local clock speed will constantly increase to 10 GHz by
the year 2011. Electrical interconnects operating at a high-frequency region have many problems to be solved, such as crosstalk, impedance matching, power dissipation, skew, and packing
density. Optical interconnection has several advantages, such as immunity to the electromagnetic interference, independency to impedance mismatch, less power consumption, and high-speed
operation. Although the optical interconnects have great advantages compared with the copper/low K interconnection, they still have some difficulties regarding packaging, multilayer technology,
signal tapping, and reworkability. In this presentation, the progress of optical interconnect for intra and inter-board levels will be presented with both passive and active components suitable
for system integration including thin film planar waveguides, vertical cavity surface emitting lasers (VCSELs), PIN photodiode array and silicon nano-photonic crystal waveguide modulators. |
| Speaker: |
Professor Ray T. Chen
Microelectronics Research Center
Analytical Development Lab
Advanced Micro Devices
University of Texas at Austin |
| Speaker Bio: |
Dr. Chen is the Cullen Trust endowed professor at UT Austin. He received his BS degree
in Physics from National Tsing-Hua University in 1980 in Taiwan and his MS degree in physics in 1983 and
his PhD degree in Electrical Engineering in 1988, both from the University of California. He joined UT
Austin as a faculty to start optical interconnect research program in the ECE Department in 1992. Prior to
his UT’s professorship, Chen was working as a research scientist, manager and director of the Department
of Electrooptic Engineering in Physical Optics Corporation in Torrance, California from 1988 to 1992.
Chen also served as the CTO/founder and chairman of the board of Radiant Research from 2000 to 2001 where
he raised 18 million dollars A-Round funding to commercialize polymer-based photonic devices. His research
work has been awarded with more than 84 research grants and contracts from such sponsors as DOD, NSF, DOE,
NASA, the State of Texas, and private industry. Chen’s group at UT Austin has reported its research findings
in more than 430 published papers including over 60 invited papers. He holds 14 issued patents. He has
chaired or been a program-committee member for more than 60 domestic and international conferences organized
by IEEE, SPIE (The International Society of Optical Engineering), OSA, and PSC. He has served as an editor
or co-editor for eighteen conference proceedings. Chen has also served as a consultant for various federal
agencies and private companies and delivered numerous invited talks to professional societies. Dr. Chen is
a Fellow of IEEE, OSA and SPIE. He was the recipient 1987 UC Regent’s dissertation fellowship and of 1999
UT Engineering Foundation Faculty Award for his contributions in research, teaching and services. Back to
his undergraduate years in National Tsing-Hua University, he led a university debate team in 1979 which
received the national championship of national debate contest in Taiwan. |
| Slides: |
Professor Ray T. Chen's Slides (pdf) |
|
| Date: |
March 22, 2007 |
| Time: |
5:30-6:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
IEEE EDC March 2007 Presentation: A New Low Frequency Noise Model for Multi-Stack Gate MOSFETs |
| Description: |
In MOSFETs, high dielectric constant (high-k) materials are developed as possible replacements for SiO2 as the gate dielectric.
Although these materials do overcome the issue of gate leakage current due to increased dielectric thickness for a given equivalent dielectric capacitance, several other problems arise.
The talk will cover noise and mobility degradation issues in high-k gate stacks. |
| Speaker: |
Zeynep Celik--Butler
Professor of Electrical Engineering
Director of Nanotechnology Research and Teaching Center
NanoFab Bld |
|
| Date: |
February 22, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
10 ns Pulsed IV Characterization of SOI and High-k Transistors |
| Description: |
Recent advances in sub-100nm semiconductor device manufacturing
process development require new measurement methods to characterize Silicon-On-Insulator
(SOI) devices and other new transistor designs, and to evaluate novel dielectrics in the pursuit
of new transistor insulator materials. These new devices heat during measurement, resulting in
significant measurement error from the device performance under 'in-use' conditions. Novel dielectrics
trap charges, making them useless as insulators. This lecture will discuss an improved solution for making f
ast pulsed measurements of these devices, resulting in accurate characterization of novel devices without
self-heating or charging effects. Called the Pulsed IV (PIV) solution, this method can easily be applied
on the lab bench or in production test for 10ns pulses to a device, resulting in accurate Id-Vg and
Id-Vd measurements of these new devices. |
| Speaker: |
Bill Verzi
Senior Member of Technical Staff
Semiconductor Process and Device Evaluation
Agilent Technologies |
| Slides: |
Bill Verzi's Slides (pdf) |
|
| Date: |
January 25, 2007 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
2007 Semiconductor Market Update |
| Speaker: |
Ken Davis
Chief Economist
Freescale |
|
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