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 Meetings
Past Events:
November 20, 2008
September 5, 2008
August 7, 2008
July 24, 2008
June 26, 2008
May 22, 2008
April 24, 2008
March 27, 2008
February 21, 2008
January 24, 2008
Back to Past Events
| Date: |
August 7, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
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| Topic: |
Unified Compact Modeling of Emerging Multiple-Gate MOSFETs |
| Description: |
In this talk, we present solution methods towards such a unified MOS compact model based on the unified regional
modeling (URM) approach, as well as paradigm shift needed for modeling future generation MOSFETs.
Regional/explicit solutions are available for the generic doped a-DG in accumulation, depletion, weak/volume-inversion
regions, and approximate solutions in inversion region for the two gate’s surface potentials. The unified solutions are
obtained with transition functions, which contain the essential physics captured in the regional solutions that are
otherwise difficult to obtain, and can be applied to terminal current/charge models with physical layer thickness and
doping scalability. When the silicon body is undoped, without assuming either carrier type being at equilibrium, both
carrier imrefs would be at non-equilibrium and, hence, bipolar conduction could result, which will be dependent on the
contact type. The results demonstrate a first step towards unification of MOS compact models for the existing bulk/SOI
and emerging MG MOSFETs with seamless transitions and selectable accuracy.
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| Speaker: |
Dr. ZHOU Xing, Ph.D.
Division of Microelectronics
School of Electrical & Electronic Engineering
Nanyang Technological University
Block S1, Room S1-B1c-95
50 Nanyang Avenue
Singapore 639798 |
| Speaker Bio: |
Xing Zhou received the B.E. degree from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees
in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively.
From 1990 to 1991, he was a research associate in the Department of Electrical Engineering, the University of
Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of CAD tools
for mixed-signal circuit simulation. From 1992 to 1995, he was a research fellow in the School of Electrical and
Electronic Engineering, Nanyang Technological University (NTU), Singapore, where he worked on Monte Carlo and
numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and
simulation. He is currently a tenured associate professor in the same school at NTU, as well as program director and lab
supervisor of the computational nanoelectronics group. His current research focuses on development of compact models
for circuit simulation for conventional and emerging nanoscale MOS devices. In November and December of 1997 as
well as in February and March 2001, he was a visiting fellow at the Center for Integrated Systems, Stanford University,
California. In January 2003, he was a visiting professor at Hiroshima University, Japan. In May 2007, he was a visiting
professor at Universiti Teknologi Malaysia. He is the founding chair of the Workshop on Compact Modeling (WCM) in
association with the Nano Science and Technology Institute (NSTI) Nanotech Conference since 2002. He was the
recipient of the 2006 NSTI Fellow award.
Dr. Zhou is an elected member of the IEEE Electron Devices Society (EDS) Administrative Committee, chair of the
EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling technical committee as
well as the Membership, Publications, and Educational Activities committees, and an EDS newsletter editor for Region
10 (Australia, New Zealand & South Asia). Since 2007 Dr. Zhou has been an editor of the IEEE Electron Device Letters.
He has served as an EDS distinguished lecturer since 2000.
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| Date: |
July 24, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Novel Graphene-based Materials, CNT Fracture Mechanics, and the Hunt for a Replacement for ITO |
| Description: |
I provide a brief update on experimental fracture mechanics of carbon nanotubes (an ongoing interest of
my research group since 1999), specifically of single walled CNTs (SWCNTs) of known diameter and chirality.
I then briefly present a project underway to improve the electrical conductivity of thin SWCNT films that
might find use as a replacement of indium tin oxide (ITO) as a transparent but conductive film. Then,
we turn to discussing graphene-based materials. Our top-down approaches [1,2] inspired physicists to
study individual layers of graphite obtained by micromechanical exfoliation, but our current approach
has been to convert graphite to graphite oxide (GO), generate aqueous colloidal suspensions containing
individual layers of GO (we call them ‘graphene oxide’), and to use these ‘graphene oxide sheets’ in
a variety of ways. For example, we have embedded individual and reduced graphene oxide sheets in
polymers such as polystyrene and evaluated their dispersion, morphology, and the electrical
percolation and thus conductivity of the resulting composites. In parallel paths, we have: (i)
undertaken studies of individual graphene oxide and reduced graphene oxide sheets, to elucidate
their chemical, optical, and electrical properties, (ii) embedded graphene oxide sheets in glass by
a sol-gel route and made electrically conductive and transparent glass coatings, and (iii) produced
'graphene oxide paper', a material with intriguing mechanical properties.
|
| Speaker: |
Prof. Rod Ruoff
Cockrell Family Regents Chair
Dept of Mechanical Engineering
The University of Texas at Austin
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| Speaker Bio: |
Prior to joining The University of Texas at Austin as a Cockrell Family Regents Chair in Mechanical
Engineering, Prof. Rod Ruoff served as Director of the Biologically Inspired Materials Institute at
Northwestern University. He has been a ‘Visiting Chair Professor’ at Sungkyunkwan University in South
Korea. He received his B.S. in Chemistry from the U. of Texas (Austin) and Ph.D. from the University
of Illinois-Urbana. He was a Fulbright Fellow at the Max Planck Institute-Goettingen, Germany. From
‘89-’90, he was a Postdoctoral Fellow at the IBM T. J. Watson Research Center in New York. Prior to
joining Northwestern in 2000, he was a Staff Scientist at the Molecular Physics Laboratory of SRI
International and Associate Professor of Physics at Washington University. His research activities
include global environment and energy; synthesis and physical/chemical properties of nanostructures
and composites; nanorobotics, NEMS, and developing new tools for biomedical research. Prof. Ruoff
has authored or coauthored ~180 refereed journal articles in the fields of chemistry, physics,
mechanics, & materials science.
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| Date: |
June 26, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Versatile Dry Release Process Dramatically Reduces MEMS Production Time |
| Description: |
The MEMS sensor market is on the cusp of exponential growth. The need for a truly robust set of dielectric,
isotropic release etch processes has never been greater. In recognizing this, we have designed a
high productivity common platform for our suite of integrated release etches and surface coating
products. This platform will enable the seamless integration of common MEMS processes, into existing
CMOS fabrication lines. Designers of products such as RF switches, pressure sensors, microphones,
speakers, accelerometers, microbolometers, inkjet heads, and others, will now have an unprecedented
degree of flexibility in rapidly creating and moving to market, their products. Industry has long
sought a robust, versatile dry, isotropic, dielectric etch process. Issues with stiction resulting
from aqueous solutions of HF are only partially mitigated through substitution of alcohols for water.
Dry Isotropic etches have historically been limited to batch systems and/or are not truly "dry".
These systems have also been limited in applications where exposed Aluminum is not present due to
corrosion problems. This novel dielectric etch allows precise control of the etch process. Oxide
films deposited by different processes requiring different process set-ups are easily accommodated.
The most common sacrificial materials are polysilicon and silicon dioxide. Historically the release
etch processing of these materials has been developed using wet etch methods, stagnant gas techniques
or gas flow processes with limited process capability. This one process fits all approach does not
address the issue that different MEMS structures require significantly different process
optimization and control. Using memsstar® systems for etching, based on controlled continuous
flow technology CCFTTM the process is optimized to the structure being etched. Controlling the
sample temperature, chamber pressure and process gas flows means that the process window
(etch rate, uniformity, selectivity) can be targeted and optimized.
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| Speaker: |
Alan Atherton |
| Speaker Bio: |
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| Date: |
May 22, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
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| Topic: |
Resistance Change Memories – Overview and challenges |
| Description: |
Resistance change memories are an exciting new type of memory which exploit the large change in resistance of
materials to store information about the state of the bit, compared to conventional charge storage based
memories. These memories not only scale well with technological nodes, but also show great promise in terms
of providing orders of magnitude faster program and erase cycling, combined with extended endurance over
standard flash memories. This talk will provide an overview of how these resistance change memories such
as Phase Change Memory (PCRAM) and Conductive Bridge Memory (CBRAM) work, their advantages, as well as
their progress and maturity to date. The challenges associated with these memories will also be
highlighted, especially those associated with applications beyond the stand alone conventional consumer
space.
|
| Speaker: |
Dr. Tushar P. Merchant
Project Leader, Advanced Non Volatile Memories
Freescale Semiconductor |
| Speaker Bio: |
Tushar Merchant completed his Master of Technology in Chemical Engineering at the Indian Institute
of Technology, Bombay and received his Ph.D. at the Massachusetts Institute of Technology also
in Chemical Engineering. He joined Motorola SPS (now Freescale) in 1994 in Tempe, Arizona where
he was responsible for developing and applying advanced computational tools and methods for process
optimization and enhancement of semiconductor manufacturing equipment. Over there, he led a number
of modeling and simulation projects to aid process development for advanced CMOS, RF, as well as
MRAM and other NVM technologies. Since moving to Austin in 2006, he has been working on the
development of advanced non volatile memories including nanocrystal, PCRAM, and CBRAM memories for
Freescale specific applications. He holds 3 U.S. patents and has been an author on over 35 articles
in journals and conference proceedings.
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| Slides: |
Tushar Merchant's Slides (pdf) |
|
| Date: |
April 24, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
An Overview of 3D Integration Technology |
| Description: |
3D integration offers inter-strata interconnect with high connectivity density, low parasitics, and
shorter lengths. This bring advantages in increased interconnect bandwidth, reduced interconnect
latency and reduced power consumption in comparison with individual packaged chips on a board or
packages with wire bonded stacked die. 3D integration can compete with, or even surpass, SoC (system
on a chip) integration in terms of interconnect performance while allowing for differentiated process
technologies for the various strata. This talk will discuss the progress made on key process
technologies for 3D integration. It will also cover some of the trade-offs between various integration
architectures. 3D integration introduces new design challenges and increases the thermal management
challenges. As with many new technologies, economics may present the most important challenge for
3D integration
|
| Speaker: |
Dr. Robert E Jones
Manager, System Interconnect Solutions
Freescale Semiconductor |
| Speaker Bio: |
Bob Jones received a B.A. in physics from Kansas State College of Pittsburg and a Ph.D. in physics
from Iowa State. He taught for a year in Germany before becoming a research associate at Lakehead
University, Ontario, Canada, where he later joined the faculty. He also was a physics professor at
the University of Colorado at Colorado Springs. Later at Inmos Corp. he led interconnect development
including early work on metal stress voiding. In 1988 he joined Motorola SPS (later spun-off as
Freescale) where his research interests have focused on new material technologies for integrated circuits
including 3D integration, silicides, ferroelectric memories, high-k dielectrics for memories and
capacitors, quantum dot memories, stacked chips, and integrated photodetectors. Bob is a Fellow of
the American Physical Society and a member of the Materials Research Society and IEEE. He holds over
30 U.S. patents and has been an author on over 100 articles in journals and conference proceedings.
|
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| Date: |
March 27, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Reliability Study of Split Gate Silicon Nanocrystal Flash EEPROM |
| Description: |
Silicon nanocrystal nonvolatile memories have been identified as one of the leading candidates to
replace floating gate nonvolatile memories for embedded microcontrollers at 90nm node and beyond [1, 2].
Split gate nonvolatile memories [3, 4, 5] employing source side injection (SSI) have the advantages
of low program current and large program window. Owing to the thin dielectrics used in these
memories, one main concern is the long term reliability such as data retention and program disturb.
Charge loss can occur from the nanocrystals through the top oxide or bottom oxide. Developing a
good understanding on the path of charge loss is important for optimizing the reliability of split
gate nanocrystal nonvolatile memories. In this talk we present a measurement based on biased
data retention to determine the direction of charge loss. Top oxide and bottom oxide thickness
can be optimized to meet long term reliability goal. A split gate nanocrystal nonvolatile memory
with large program window, while demonstrating excellent data retention and program disturb
characteristics is also presented.
|
| Speaker: |
Cheong Hong
Technology Solutions Organization
Freescale Semiconductor, Austin, Texas |
| Speaker Bio: |
Cheong Min Hong studied electrical engineering at Arizona State University from 1991 to 1994 and
graduated with a B.S. degree, summa cum laude. After graduation, he joined Motorola’s wireless
communication research and development group. From 1995 to 1999, he pursued graduate studies at
Princeton University and obtained M.A. and Ph.D. degrees in electrical engineering. At Princeton,
he pioneered the method of jet printed copper metallization for thin film transistors. Since
joining Freescale Semiconductor in 2000, he has worked extensively in the device engineering and
process integration of advanced flash memories.
|
| Slides: |
Cheong Hong's Slides (pdf) |
|
| Date: |
February 21, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Advanced Transistor Structures for 22nm Technology |
| Description: |
Since the 1990's, research on multi-gate transistor has been pursued by many companies,
universities, and consortium around the world. It has been shown that the multi-gate MOSFET
can provide high drive current, good electrostatic channel control, and undoped channels at
gate lengths of 20-30 nm. According to the ITRS roadmap, multi-gate transistor is needed for
32nm and beyond. With Intel announcement that products using 45nm technology will be available
by the end of 2007, 32 nm technology development is already on-going and we could expect that
32nm technology product maybe available sometime in late 2009 or early 2010, and transistor
structure evaluation / selection for 22nm technology node is already starting at major
semiconductor companies. This presentation will give a brief discussion on multi-gate
transistor performance, an overview of the main stream multi-gate transistors manufacturability,
and discuss what is required of multi-gate transistor to meet 22nm product design and high
volume production.
|
| Speaker: |
Thuy Dao
Freescale Semiconductor, Austin, Tx |
| Speaker Bio: |
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| Slides: |
Thuy Dao's Slides (zip) |
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| Date: |
January 24, 2008 |
| Time: |
6:00-7:30pm - Seminar |
| Location: |
Sematech
(view map)
Room F-C
|
| Topic: |
Solar Cell based on nanoparticles and polymers. |
| Description: |
|
| Speaker: |
Lawrence Dunn |
| Speaker Bio: |
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Thuy Dao