Solid-State-Circuits / Circuits and Systems
Joint Chapter
Central Texas Section
Joint Chapter
Central Texas Section
September
2009:
May 2009:
April 2009:
Feb 2009:
Topic/Title The Annual Review of the ISSCC
Speaker A panel of:
Dr. Betty Prince - Memories
Mike Seningen - Digital
Lawrence Regan - RF
Date/Time Tuesday March 10th, 6:30pm
December 2008:
Abstract: This talk will start by analyzing the trade-offs between the two key metrics, power and performance, in modern digital circuits, and offer insights into ways to optimize the design by the proper setting of various design "knobs" such as Vdd, Vth, and sizing. The two-metric sensitivity-based optimization will then be expanded to multiple metrics, such as reliability, thermals, area, cost, etc., and will be followed by specific design methods for multi-threshold and multi-voltage circuits, adaptive circuit design using body biasing, temperature-aware design, optimal voltage scheduling, and bus encoding. The multi-threshold design methods will include a novel sleep mode state-preserving flip-flop, the multi-voltage circuit methods will include a single threshold high-performance low leakage circuit solution, the adaptive circuit design methods will include body-biasing schemes to compensate for thermal and aging effects, the optimal voltage scheduling scheme will explain why procrastination can actually save power for tasks with uncertain finishing times, while bus encoding can save power by reducing switching on global interconnect. This talk is the result of more than 100 publications, 6 patents, 8 PhD and 12 MS students, 12 years of academic and 8 years of industry experience.
Presenter:
Mircea R. Stan received the Ph.D. (1996) and M.S. (1994) degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from "Politehnica" University in Bucharest, Romania. Since 1996 he has been with the Department of Electrical and Computer Engineering at the University of Virginia, where he is now full professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, and nanoelectronics. He has more than eight years of industrial experience, has been a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He has received the NSF CAREER award in 1997 and was a co-author on best paper awards at GLSVLSI 2006, ISCA 2003 and SHAMAN 2002. He was the chair of the VLSI Systems and Applications Technical Committee (VSA-TC) of IEEE CAS in 2006-2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for NanoNets 2007 and ISLPED 2005, and on technical committees for numerous conferences. He has been an Associate Editor for the IEEE Transactions on Circuits and Systems Systems I in 2004-2007 and for the IEEE Transactions on VLSI Systems in 2001-2003. He has also been a Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Solid-State Circuits Society (SSCS) in 2007-2008, and for the IEEE Circuits and Systems (CAS) Society in 2004-2005. Prof. Stan is a senior member of the IEEE, a member of ACM, IET (former IEE), and also of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.
November 2008:
Abstract: We present an on-chip word line (WL) dual supply system prototype for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficient charge transfer and energy conversion, boosting unregulated rails to 1.8x supply. At vdd=1V, regulated high (1.5 to 1.7V) and low (-0.3 to -0.6V) levels ensure WL overdrive and cell turn-off, respectively, with rippling <±35mV and maintenance power <780uW/2Mb-DRAM. This WL supply system supports >2GHz AC array access and can endure excessive DC load.
October 2008:
Topic: Electric Vehicle Conversions
Presenter: Aaron Choate, Founder ReVolt
Date/Time: Tuesday, October 14, 2008, 6:30PM
Cost: none
Reservations: not required
Location: UT Campus - ACA 1.104.
For more information: http://www.revoltcustomelectric.com/
September 2008h
Topic: Digital Multiplier Performance
Presenter: Dr. Earl Swartzlander, Professor at UT Austin
Date/Time: Tuesday, September 9, 2008, 6:30PM
Cost: none
Reservations: not required
Location: UT Campus - ACES 2.402 Auditorium
April 2008
| Title: | Being Young, Being Digital: Some Observations on Young People's Use of Social Media | |
| Presenter: |
Prof.
S. Craig Watkins The University of Texas at Austin Department of Radio-Television-Film |
|
| Date: |
Tuesday, Sept 8th,
6:30PM, AVAYA Auditorium (ACE 2.302) on UT Campus |
|
|
|
Abstract: |
From
the moment new communication technologies began to infiltrate American
homes, young people have been among the early explorers and early
adopters of computers and the Internet. Today, teens and young
adults are credited for the ascent of social media platforms like
MySpace, Facebook, and YouTube. The social web has been variously
characterized as empowering, participatory, and communal. Drawing
from original research including survey data and in-depth interviews
this talk considers the rise and use of social media. Designed
more as a public discussion about the steadily evolving role of social
media technologies in our lives the paper considers three
questions. First, how dominant is social media in young people's
lives? Second, what are young people doing with new communication
technologies? The third question considers the social impact and
consequences of social media. Prof. Watkins's talk about his work on YouTube: http://www.youtube.com/watch?v=YtLc2qkLM2E |
| Bio: |
S. Craig Watkins teaches in the departments of Radio-Television-Film and Sociology and the Center for African and African American Studies at the University of Texas at Austin. His new book, The Young and the Digital: What the Migration to Social Network Sites, Games, and Anytime, Anywhere Media Means for Our Future (Beacon) explores young people's dynamic engagement with social media, online games, and mobile phones. Watkins participated in the MacArthur Foundation Series on Youth, Digital Media and Learning. He has been invited to be a Research Fellow at the Center for Advanced Study in the Behavioral Sciences (Stanford). Currently, he is launching a new digital media research initiative that focuses on the use and evolution of social media platforms. |
May 2009:
| Title: | Chip Reveal 3D | |
| Presenter: |
Dr. Jerzy Gazda of Cerium Labs | |
| Date: |
Tuesday, May 12th, 6:30PM, ENS 306A on UT Campus | |
|
|
Abstract: |
Dr. Jerzy Gazda will talk about their "Chip Reveal 3D" for reverse engineering and litigation support |
April 2009:
| Title: |
A Sub 2W Low Power IA Processor for Mobile Internet Devices in 45nm Hi-K Metal Gate CMOS | |
| Presenter: |
Gian Gerosa, Intel Austin | |
| Date: |
Tuesday, April 14th, 6:30PM, ENS 306A on UT Campus | |
|
|
Abstract: |
This presentation describes a low power Intel® Architecture (IA) processor specifically designed for Mobile Internet Devices. The design relies on high residency in a new low-power state in order to keep average power and idle power below 220 and 80 mW, respectively. The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32KB instruction and 24KB data L1 caches, independent integer and floating point execution units, x86 front end execution unit, a 512KB L2 cache with in-line ECC and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus. The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45nm CMOS process with optimized transistors for low leakage. Several circuit techniques to reduce dynamic and leakage power will be presented. Maximum thermal design power consumption is measured at 2W at 1. |
Feb 2009:
Topic/Title The Annual Review of the ISSCC
Speaker A panel of:
Dr. Betty Prince - Memories
Mike Seningen - Digital
Lawrence Regan - RF
Date/Time Tuesday March 10th, 6:30pm
December 2008:
IEEE Solid State Circuits Distinguished Lecturer Professor Mircea R. Stan of the University of Virginia on the topic of
High Performance Low Power VLSI Circuit Design
in conjunction with the University of Texas VLSI Symposium series.
Tuesday Dec 9th, 630pm ACES 2.402
Pizza and beverages will be provided.
Abstract: This talk will start by analyzing the trade-offs between the two key metrics, power and performance, in modern digital circuits, and offer insights into ways to optimize the design by the proper setting of various design "knobs" such as Vdd, Vth, and sizing. The two-metric sensitivity-based optimization will then be expanded to multiple metrics, such as reliability, thermals, area, cost, etc., and will be followed by specific design methods for multi-threshold and multi-voltage circuits, adaptive circuit design using body biasing, temperature-aware design, optimal voltage scheduling, and bus encoding. The multi-threshold design methods will include a novel sleep mode state-preserving flip-flop, the multi-voltage circuit methods will include a single threshold high-performance low leakage circuit solution, the adaptive circuit design methods will include body-biasing schemes to compensate for thermal and aging effects, the optimal voltage scheduling scheme will explain why procrastination can actually save power for tasks with uncertain finishing times, while bus encoding can save power by reducing switching on global interconnect. This talk is the result of more than 100 publications, 6 patents, 8 PhD and 12 MS students, 12 years of academic and 8 years of industry experience.
Presenter:
Mircea R. Stan received the Ph.D. (1996) and M.S. (1994) degrees in Electrical and Computer Engineering from the University of Massachusetts at Amherst and the Diploma (1984) in Electronics and Communications from "Politehnica" University in Bucharest, Romania. Since 1996 he has been with the Department of Electrical and Computer Engineering at the University of Virginia, where he is now full professor. Prof. Stan is teaching and doing research in the areas of high-performance low-power VLSI, temperature-aware circuits and architecture, embedded systems, and nanoelectronics. He has more than eight years of industrial experience, has been a visiting faculty at UC Berkeley in 2004-2005, at IBM in 2000, and at Intel in 2002 and 1999. He has received the NSF CAREER award in 1997 and was a co-author on best paper awards at GLSVLSI 2006, ISCA 2003 and SHAMAN 2002. He was the chair of the VLSI Systems and Applications Technical Committee (VSA-TC) of IEEE CAS in 2006-2007, general chair for ISLPED 2006 and for GLSVLSI 2004, technical program chair for NanoNets 2007 and ISLPED 2005, and on technical committees for numerous conferences. He has been an Associate Editor for the IEEE Transactions on Circuits and Systems Systems I in 2004-2007 and for the IEEE Transactions on VLSI Systems in 2001-2003. He has also been a Guest Editor for the IEEE Computer special issue on Power-Aware Computing in December 2003 and a Distinguished Lecturer for the IEEE Solid-State Circuits Society (SSCS) in 2007-2008, and for the IEEE Circuits and Systems (CAS) Society in 2004-2005. Prof. Stan is a senior member of the IEEE, a member of ACM, IET (former IEE), and also of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.
November 2008:
Topic: On-Chip Dual
Supply Generation for embedded DRAM
Presenter: Dr. JB Kuang, IBM Austin Research Lab
Date/Time: Tuesday,
Nov. 11, 2008, 6:30PM
Cost: none
Reservations: not
required
Location: UT Campus -ACA 1.104.
Abstract: We present an on-chip word line (WL) dual supply system prototype for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficient charge transfer and energy conversion, boosting unregulated rails to 1.8x supply. At vdd=1V, regulated high (1.5 to 1.7V) and low (-0.3 to -0.6V) levels ensure WL overdrive and cell turn-off, respectively, with rippling <±35mV and maintenance power <780uW/2Mb-DRAM. This WL supply system supports >2GHz AC array access and can endure excessive DC load.
Bio: JB
Kuang is a research staff member at
the Exploratory VLSI department of the Austin Research Laboratory. He
worked on various product development and research projects since
joining IBM in 1990. He received BS, MS, PhD from National Taiwan,
Columbia, and Cornell University, all in electrical engineering.
Topic: Electric Vehicle Conversions
Presenter: Aaron Choate, Founder ReVolt
Date/Time: Tuesday, October 14, 2008, 6:30PM
Cost: none
Reservations: not required
Location: UT Campus - ACA 1.104.
For more information: http://www.revoltcustomelectric.com/
September 2008h
Topic: Digital Multiplier Performance
Presenter: Dr. Earl Swartzlander, Professor at UT Austin
Date/Time: Tuesday, September 9, 2008, 6:30PM
Cost: none
Reservations: not required
Location: UT Campus - ACES 2.402 Auditorium
SSC/CAS
Chapter is sponsoring Austin Conferce on Integrated Systems
& Circuits hold on May 7-9, 2008.
The 3rd Annual Austin
Conference on Integrated Systems & Circuits will again serve as a
forum for the dissemination of technical information and advances in
electronic technology at chip, board and system levels, covering
design, CAD methodology, and test. CEO's of two of America's fastest
growing semiconductor design companies will be giving keynote
addresses: Dr. Necip Sayiner of Silicon Labs and Dr. Jason Rhode of
Cirrus Logic's give their perspective on growing in a tough market.
April 2008
Topic/Title:
What Every Architect
Should Know About Technology
Speakers: Dr.
Sani Nassif
Manager, Tools and Technology Department
IBM Austin Research Lab
Date/Time: Tuesday, April 8, 2008,
6:30PM
Cost:
none
Reservations:
not required
Location: UT Campus - ACES 2.402 Auditorium
Abstract:
Different from most engineering disciplines, in IC design we do not
usually do "full" prototyping. We may try out a few parts of a design
on test chips but we do not do full-scale prototyping as would happen
-for example- for a car. We rely completely on "models" of the
technology to help us predict and assure the performance of our chips.
As we have crossed from 90 to 65 and now to 45nm, these models are
starting to break down. We have had to add vast amounts of complexity
to the fabrication process in order to keep up with scaling. In fact,
performance improvement has come more from innovation (OPC/RET, Cu,
SOI, Stress) than from straight feature size reduction. This complexity
exhibits itself most blatantly in the drastic increase in the number of
design rules used to define the technology. We are seeing 10x increases
in the number of rules going from 250 to 45nm. So what is needed is
better models, and better penetration of these models into the CAD
flow. I posit that DFM thus far has been solely about putting
manufacturing awareness in design, and that this awareness is only felt
at the very lowest levels of typical digital design (layout and
schematic). We need manufacturing awareness to move up the stack to the
micro-architecture level, in order to best leverage the limited degrees
of freedom available for circuit adaptation.
Bio:
Sani received his PhD from Carnegie Mellon University in the eighties.
He worked for ten years at Bell Laboratories on various aspects of
design and technology coupling including device modeling, parameter
extraction, worst case analysis, design optimization and circuit
simulation. He joined the IBM Austin Research Laboratory in January
1996 where he is presently managing the tools and technology
department, which is focused on design/technology coupling and includes
activities in: model to hardware matching, simulation and modeling,
physical design, statistical modeling, statistical technology
characterization and similar areas.
Topic/Title:
Ranger Supercomputer (Austin
Forum)
Speaker: Drs. Jay Boisseau, Karl Schulz, and Omar Ghattas
Date and Time: Wednesday April 2nd, 2008 6:30 PM
Cost: none
Reservations: not required
Meeting Location: Pickle Research Center - ROC, Bldg. 196, Seminar room 1.603
We are also organizing a tour for Range supercomputer on Wednesday June 4 5:15pm at Pickle Research Center. Please email seningen@ieee.org for more information.
Speaker: Drs. Jay Boisseau, Karl Schulz, and Omar Ghattas
Date and Time: Wednesday April 2nd, 2008 6:30 PM
Cost: none
Reservations: not required
Meeting Location: Pickle Research Center - ROC, Bldg. 196, Seminar room 1.603
We are also organizing a tour for Range supercomputer on Wednesday June 4 5:15pm at Pickle Research Center. Please email seningen@ieee.org for more information.
March 2008
A Review of ISSCC 2008
Matt Felder --- Analog, Michael Runas --- Digital, Lawrence Regan -- RF/Microwave
Matt Felder --- Analog, Michael Runas --- Digital, Lawrence Regan -- RF/Microwave
January 2008
Variation
Robustness
for Analog/Mixed-Signal, Custom Digital and Memory Design
Patrick G. Drennan, PhD Chief Technology Officer of Solido Design Automation
Patrick G. Drennan, PhD Chief Technology Officer of Solido Design Automation
February 2004
Physical
Synthesis for Nanometer Designs
Dr. David Z. Pan
Electrical and Computer Engineering Department
& Computer Engineering Research Center
The University of Texas at Austin
http://www.ece.utexas.edu/~dpan
Dr. David Z. Pan
Electrical and Computer Engineering Department
& Computer Engineering Research Center
The University of Texas at Austin
http://www.ece.utexas.edu/~dpan
Abstract
As CMOS scales into nanometer
dimensions, IC designs are more and more interconnect-dominated
(ITRS’03). The resulting design closure has been a central problem for
electronic design automation, as seen by enormous efforts from both
academia and industry. Meanwhile, as CMOS scaling continues, power is
becoming a key design limiter. Voltage scaling with multiple supply and
threshold voltages is one of the most effective ways to reduce power,
but it may perturbate physical layout and timing, thus shall be
addressed during the design closure as well. To reduce the turn around
time and improve performance/yield, predictive modeling shall also be
developed. In this talk, I will discuss several key issues related with
nanometer physical design closure, focusing on performance, power, and
predictability (3P). The results on the performance-driven design
closure will be presented under an interconnectcentric paradigm which
emphasizes early interconnect estimation and planning. I will also
present some results on multiple Vdd/Vth for low power optimization.
Although tremendous efforts have been put, there is still significant
gap between what tools can provide today and what the optimal solution
is. Such gap seems to increase with ever-growing design complexities
and technology challenges (e.g., leakage, noise, uncertainty). I will
address future research directions before concluding the talk.
Biography
Dr. David Pan is currently an assistant professor at Electrical and Computer Engineering Department, the University of Texas at Austin, where he joined in August 2003. He received his Ph.D. (with honor) in computer science from UCLA in December 2000. Prior to UT, he was a Research Staff Member at IBM T. J. Watson Research Center. His research interests include nanometer VLSI physical design closure, low power design with novel circuitry and CAD, interconnect modeling, synthesis and planning, design space exploration of SoC, SoP and embedded systems. He has published over 20 technical papers and has 6 U.S. patents issued or pending. He is a program committee member for ICCAD, ISPD, ASPDAC, GLSVLSI, and SLIP. Dr. Pan received the Best Paper in Session Award from SRC Techcon 1998, IBM Research Fellowship for 1999-2000, Dimitris Chorafas Foundation Award for research excellence in 2000, SRC Inventor Recognition Award in 2000, and Outstanding Ph.D. Award from UCLA Computer Science Department in 2001. At IBM, he was a key research member of Placement Driven Synthesis (PDS), IBM's flagship design closure tool, which won IBM Research 2002 Outstanding Accomplishment. He received IBM Bravo Award in 2003 for contributions to PDS. He served as an industrial mentor to a number of SRC sponsored research projects while at IBM.
Last updated: February 16, 2004
© 2004 IEEE Central Texas Solid-State Circuits / Circuits and Systems joint chapter
Biography
Dr. David Pan is currently an assistant professor at Electrical and Computer Engineering Department, the University of Texas at Austin, where he joined in August 2003. He received his Ph.D. (with honor) in computer science from UCLA in December 2000. Prior to UT, he was a Research Staff Member at IBM T. J. Watson Research Center. His research interests include nanometer VLSI physical design closure, low power design with novel circuitry and CAD, interconnect modeling, synthesis and planning, design space exploration of SoC, SoP and embedded systems. He has published over 20 technical papers and has 6 U.S. patents issued or pending. He is a program committee member for ICCAD, ISPD, ASPDAC, GLSVLSI, and SLIP. Dr. Pan received the Best Paper in Session Award from SRC Techcon 1998, IBM Research Fellowship for 1999-2000, Dimitris Chorafas Foundation Award for research excellence in 2000, SRC Inventor Recognition Award in 2000, and Outstanding Ph.D. Award from UCLA Computer Science Department in 2001. At IBM, he was a key research member of Placement Driven Synthesis (PDS), IBM's flagship design closure tool, which won IBM Research 2002 Outstanding Accomplishment. He received IBM Bravo Award in 2003 for contributions to PDS. He served as an industrial mentor to a number of SRC sponsored research projects while at IBM.
Last updated: February 16, 2004
© 2004 IEEE Central Texas Solid-State Circuits / Circuits and Systems joint chapter