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Technical
Seminar |
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Tutorial on Practical
Power-Delay Design Trade-offs |
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DATE/TIME
Friday, March 11, 2011 (9:00am to 11:00am) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 8:45am for security sign-in and escort. |
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to
steven.martin@avagotech.com. |
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ABSTRACT |
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This tutorial
will be an encore of ISSCC 2011 Tutorial T6. Design of high-speed,
power-optimized circuits is an increasingly large part of the digital
circuit designer’s responsibilities. Circuit and block design trade-offs
between delay, active, and leakage power are vital to meeting power and
delay goals. This tutorial begins with basics of digital circuit delay
and power consumption. Discussion turns to methods for reducing power
and delay, active/leakage power trade-offs, and a review of circuit
styles and their power-delay characteristics. Design and synthesis tools
and methods to meet timing and power goals will also be discussed.
Finally, system-level power management problems, solutions, and
trade-offs are discussed. |
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TIMOTHY
FISCHER (AMD, Fort Collins, CO)
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Tim Fischer
has worked
in high-speed digital circuit design for 22 years. He earned the MS in
Computer Engineering from the University of Cincinnati in 1989. Tim then
worked for Digital Equipment in Hudson, MA until 1998 designing VAX and
Alpha CPUs. From 1998 to 2006, he worked on Itanium CPU design with
Hewlett-Packard and Intel in Fort Collins, CO. Since 2006 Tim has been
an AMD Fellow working on CPU circuit design and methodologies. His
interests include high-speed CMOS circuits, latching/clocking
structures, and power-efficient design. |
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