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Technical
Seminar |
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Resonant Clock Design for a Power-efficient
High-volume x86–64 Microprocessor |
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DATE/TIME
Friday, May 18,2012 (10:00 to 11:00am) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 9:45am for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Register at
https://gomartin.net/sscs/2012/rsvp_2012_05_18.htm |
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ABSTRACT |
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This presentation is an extended encore of a
paper recently delivered at the 2012 International Solid-State Circuits
Conference (ISSCC) in San Francisco, CA.. |
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AMD's 4+ GHz x86–64 core codenamed
“Piledriver” employs resonant clocking to reduce clock distribution
power up to 24% while maintaining a low clock-skew target. To support
testability and robust operation at the wide range of operating
frequencies required of a commercial processor, the clock system
operates in two modes: direct-drive and resonant.
Leveraging favorable factors such as the availability of two thick
top-level metals, high operating frequency, clock-load density, and the
existing clock-design methodology, the resonant clock mode was designed to enable
both reduced average power dissipation and improved
peak-power-constrained performance, with minimal area impact. This work
represents a volume production-enabled implementation of resonant clock
technology, and is plan of record for mid-2012 product offerings. |
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PRESENTATION SLIDES
pdf |
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REFERENCE (IEEE copyright) |
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DR. VISVESH
SATHE (AMD, Fort Collins, CO) |
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Visvesh Sathe (S'02-M'07) received the B.Tech.
degree in electrical engineering in 2001 from the Indian Institute of
Technology, Bombay, India, and the M.S. and Ph.D. degrees in electrical
engineering and computer science in 2004 and 2007 respectively from the
University of Michigan, Ann Arbor. While at Michigan, his research
focused on low-energy circuit design with particular emphasis on
resonant-clocked digital design. He has held internship positions at
the IBM T.J Watson Research Center and Cyclos Semiconductor, a start-up
focusing on resonant-clocked microprocessors. In 2007, he joined the
power management group at Advanced Micro Devices, Fort Collins, CO,
where he is now Member of Technical Staff exploring and implementing
power reduction techniques for next-generation processors. Dr. Sathe
has authored 13 technical publications and two US patents. |
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SAM
NAFFZIGER (AMD, Fort Collins, CO)
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Sam
Naffziger received the BSEE degree from the California Institute of
Technology, Pasadena, CA, in 1988, and the MSEE degree from Stanford
University, Stanford, CA, in 1993. He has over 22 years experience in
microprocessor design, having led the implementation of PA-RISC, Itanium
and AMD processors working for Hewlett Packard, Intel and AMD. He
joined AMD in 2006, helping start the Mile High Design Center in Fort
Collins, CO where he has been responsible for power and frequency
optimization of mainstream processors and is the power efficiency
architect for AMD’s products. He holds 96 U.S. patents on processor
circuits and architecture and has over 25 IEEE publications and
presentations. Mr. Naffziger chaired the Digital subcommittee of the
International Solid-State Circuits Conference for 5 years, was Associate
Editor for the JSSC, and is a Corporate Fellow at AMD. |
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