2004 IEEE-BCS Events
2004 Annual Banquet
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Green Destiny: A 240-Node Computer Cluster in
One Cubic Meter Distinguished Speaker: Wu-chun Feng of the Los Alamos
National Laboratory. Winner 2004 International Super-Computer
Conference Award. ABSTRACT: In this talk, Dr. Feng will
present a new twist to the Beowulf cluster: the Bladed Beowulf. In
contrast to traditional Beowulfs, Dr. Feng's Bladed Beowulf, dubbed
Green Destiny, uses Transmeta processors in order to keep thermal
power dissipation low and reliability and density high while still
achieving comparable performance to Intel- and AMD-based clusters
when their processors run at the same clock rate. Although
performance and price/ performance have been (and will continue to
be) important metrics in high-performance computing, Dr. Feng
believes that the issues of efficiency, reliability, and availability
will be *the* issues of this decade. Bigger and faster machines will
not be good enough anymore. Consequently, he proposes a new
performance metric, Total Price/Performance Ratio (ToPPeR), to
evaluate highperformance computing systems. However, due to the
hidden and institution-specific costs in the ToPPeR metric, two
alternative (but more concrete) performance metrics that are related
to efficiency, reliability, and availability are also proposed:
performance/power ratio ("power efficiency") and
performance/space ratio ("space efficiency"). Dr. Feng will
then present empirical data for the aforementioned metrics via a
cosmology code and a bioinformatics code. BIOGRAPHY: Wu-chun Feng is a technical staff
member and team leader of RADIANT in the Computer & Computational
Sciences Division at Los Alamos National Laboratory. He received a
B.S. in Electrical & Computer Engineering and Music (Honors) and
an M.S. in Computer Engineering from the Pennsylvania State
University in 1988 and 1990, respectively. He earned a Ph.D. in Computer
Science from the University of Illinois at Urbana-Champaign in 1996.
Dr. Feng joined Los Alamos National Laboratory in 1998, where he as
been conducting research in high-performance networking and
computing. In that span of time, he has established a respected
record of over 50 journal and conference publications and has given
over 20 invited talks and colloquia. Most recently, CNN and the New
York Times reported on his revolutionary new supercomputer dubbed
Green Destiny, a supercomputer that is part of Dr. Feng's larger
"Supercomputing in Small Spaces" project. (Technical papers
about Green Destiny appear in ICPP 2002, IEEE Cluster 2002, and SC
2002.) In addition, he is known for his research in high-performance
networking on clusters and grids as well as tools to enable the
monitoring and optimization of high-performance computing platforms. |
Idaho High Performance Computing Workshop
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System architects, application developers and
science practitioners from Boise State, Idaho State, the U. of Idaho,
Idaho Engineering Lab, Dept. of Environmental Quality and local
Industry will discuss their Grid and Cluster implementations and the
applications running on them. |
August 2004 Techncal Seminar
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RTL Design Practices from a Firmware Perspective Gary Stringham, Hewlett Packard Co. ABSTRACT: Too often, designs of FPGAs,
ASICs, ASSPs, and other chips have negative impact on firmware development,
causing schedule delays and lower quality in the embedded products
being developed for market. Once a chip is in silicon form, it is
generally too late to make RTL changes, causing the firmware engineer
to attempt to put in workarounds in firmware to salvage the
chip. This presentation discusses design practices in several
areas of RTL design, such as documentation, registers, interrupts,
aborts, and test hooks. As the RTL engineers follow the
concepts taught in this class in the design of their chips, the
firmware engineers will be able to more quickly develop the code,
especially while debugging the interaction between the chip and
firmware. This presentation would also be of benefit to
firmware engineers who develop firmware to control chips.
Learning these concepts will help them develop better firmware faster
and help influence the RTL engineers in the design of the chips. BIOGRAPHY: Gary Stringham has been with
Hewlett-Packard Co. for 21 years with the last 13 years being in
firmware design for HP LaserJet printers. He has established
device driver standards and has influenced many design changes in
custom ASICs. Gary has been awarded four patents and has over
20 pending. He is writing a book, "RTL Design Practices."
He is a frequent and popular speaker. Gary holds a BSEE from
Brigham Young University and an MSEE from Utah State University. |
June 2004 Technical Seminar
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Abstract Patterns and Artifacts and Iterations
(Oh My) Darrel Carver, Senior Technical Member, Micron Technology,
Inc. ABSTRACT: It has been estimated that
formal design and code inspections combined with long-range
technology planning can result in over a more than 3,000% return on
investment over a three- year period. This presentation will cover
how Micron's Facilities IS Team (FIST) is implementing design
patterns and short, fixed -length iterations to implement long-range
technology planning and formalize the design and code review process.
BIOGRAPHY: Darrel is a Software Engineer at
Micron and a Senior Member of their Technical Career Ladder. He has
been at Micron almost 7 years and has been in the industry about 20
years. He has owned his own consulting company (a Microsoft Certified
Solution Provider) and worked for a number of other companies around
the US. He is a certified Executrain trainer and was one of the first
Microsoft Certified Professionals in 1995. |
April 2004 Techncal Seminar
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Semiconductor Packaging Evolution: Changes and
Constants Larry Moresco, President, DFX Solutions, Inc. ABSTRACT: From a single transistor made
from a chunk of semiconducting material in a vacuum tube, to 10s of
millions of transistors on a small slice of silicon, the obstacles
facing packaging engineers continue to be challenging. Today
packaging engineers work with flip chip ball grid arrays,
systems on a chip, systems in a package, chip scale packages, and
stacked die packages, while developing wafer scale package
technologies to push the envelope of what is possible. Stating the goal is easy: make it cheaper,
smaller, and faster than anything available today. Physics,
materials, and politics present barriers to achieving that
goal. Throw in manufacturing evolution from a solely in-house
endeavor, to one combined with external world wide contract manufacturing
organizations for high volume low cost production, and the allowable
manufacturability margins of error plummet. This presentation will discuss the changes, the
constants, and the challenges faced by semiconductor packaging
engineers while taking a glimpse into the future of this demanding
engineering field. BIOGRAPHY: After receiving his Ph.D. in
Mechanical Engineering from the University of California, Larry
started his career in electronic packaging at Hewlett Packard's
Computer Systems Division in Cupertino. In 1980 he designed and
qualified HPs first wirebonded laminate pin grid array package,
replacing a more expensive ceramic PGA. He went on to develop
ceramic and thin film polymer based single and multichip package
technologies at HPLabs in Palo Alto, where his last job was reporting
to the Director of HPLabs as the technical member of HP's Strategic
Planning staff. He was then hired as the Director of R&D to
start a subsidiary in California of Fujitsu Japan's Computer
Technology Division. The technologies researched and
developed by this subsidiary are now in Fujitsu's servers. At
Micro Module Systems, as the VP of Engineering, Larry developed
multi-chip module technologies for computing and high performance
testing platforms. Production customers included Ross, Intel,
and Motorola. He then was hired by Intel as their Mobile
Packaging Manager, overseeing the development of processor and
support chip packaging for Intel's Mobil Products Group. At the
time he left Intel to start DFX Solutions in Eagle, he worked for
Intel's Assembly Technology Development group in Chandler, AZ, as
Manager of Non-CPU Packaging including: flash, chipset, graphics, and
networking chip designs. Currently, he provides engineering
expertise for the design, process development, appraisal and control
required for volume manufacturing of integrated circuit
packages. He is the author of 24 US electronic packaging
patents. |
February 2004 Technical Seminar
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Is a Patent Worth More Than The Paper It's
Printed On? Bob Frohwerk, Your Intellectual Property
Matters, LLC (http://www.youripmatters.com/) ABSTRACT: Of the many ways to protect your
ideas, Patents are often the first to come to mind. Do you have
ideas that qualify for Patent protection? As an Engineer or
Scientist, your ideas may belong to your employer who may have gotten
a Patent for you without your understanding much of what was
involved. This presentation should help you to better understand
what is patentable, where and when, and how Patents come to be
granted. We will discuss some of the special issues surrounding
U.S. and foreign Software Patents. You may also recognize why
your employer chose not to seek a Patent for your world-changing idea
and what alternatives there might have been. Bring your
IP-related questions for a lively and informative discussion.
Recent Patents of special interest may be considered as time permits. BIOGRAPHY: With a BS in Engineering from Caltech
(Pasadena, CA), Bob Frohwerk began his career at a little known
startup, being hired into Intel by Dr. Andy Grove himself, as
Test Engineer for the world's first Microprocessor and EPROMs.
Accepting an invitation to join Hewlett-Packard, he developed Signature
Analysis and described it in an industry classic paper in the HP
Journal. Similar techniques carried into disk and tape systems for
modulation codes, error correction, and data compression (working
with Dr. Abraham Lempel). Bob then put the first Scalable fonts into
HP LaserJet Printers and extended them to synthetic fonts that are
created on-the-fly. After more than 30 years as an R&D
Engineer and Manager in the Electronics Industry, Bob is now a
Registered Patent Agent. Admitted to practice before the U.S. Patent
& Trademark Office, he applies his broad experience to assist
other Inventors by writing Patents to protect their ideas ranging
from IC Wafer Fab through Portable Measurement, Navigation and
Communication Devices. |
