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January 2008 Chapter Meeting                                                                

 

When:

Wednesday, January 30, 2008, 6:30pm - 8:30pm (RSVP for food/drinks req'd asap).

 

Meeting Place:  University of Portland Engineering Hall room #216 (see building #22 on the Campus Map provided below), 5000 Willamette Blvd. Portland, OR.  The most convenient place to park will be behind building #22.

 


 

 Map to University of Portland

Campus Map of the University of Portland

 

 

Subject:

 

HFSS, IE3D, CST, SONNET, and MSM(?) for Circuit and Package Modeling

Fred Weiss

Avnera Corporation

 Abstract

 During the 1980’s we began to see a limited number of commercial products for analyzing and simulating the behavior of electromagnetic structures. These were able to handle structures of very limited complexity, they were difficult to use, and they were expensive. Fast-forward to 2008: Today we have a myriad of such tools which are able to handle structures of considerably greater complexity than their earlier cousins, but which are still relatively difficult to use, and still relatively expensive.

 In contrast, the microwave community has for many, many years used the technique of Mechanical Scale Modeling to aid in the design of relatively simple 2- and 3D structures such as compensated vias, couplers, waveguides, and the like. This technique uses scaling relationships to correlate the electrical characteristics of macroscopic – and, therefore, easily manipulated – models to those of the actual, much smaller, structures used on circuit boards and hybrids. The result is essentially an analog simulator that gives one the ability to quickly, accurately, and inexpensively develop microwave components.

 An interesting aspect of mechanical scale modeling is that it can be applied to a much broader set of problems than microwave component design. In particular, it has been found to be useful, inexpensive, and relatively fast tool for a variety of IC-related design tasks including package modeling, inductor design, and even on-chip IC interconnect analysis. This talk will describe the author’s experiences with this technique, including a brief review of the theoretical underpinnings as well as limitations of the method, model construction and measurement techniques, results, and examples of actual hardware.

 

About the Speaker:

Brief bio for Fred Weiss

 Fred Weiss is the Avnera Fellow for RF and Analog Architecture and has been with that company since August of 2004, during which time he has been primarily involved in the development of a variety of RF, analog, and data conversion circuits used in Avnera’s wireless products. Fred holds a Bachelor’s Degree in Physics from the University of Washington (Seattle), and MSEE and PhD degrees in Electronic Engineering from the University of California at Los Angeles. Since finishing graduate school in 1981 he has been privileged to work for Tektronix Laboratories, TriQuint Semiconductor, Analog Devices, and Avnera, over the course of which employment he has had the pain and pleasure of designing high speed data conversion, RF, synthesizer, and RF power control products in Bipolar, CMOS, BiCMOS, SiGe, and GaAs MESFET IC process technologies. He was the principal designer of the TriQuint GigaDACÔ product line of gigasample/second 8- and 14-bit DACs for video and signal synthesis applications, and is the author or co-author of 8 patents and16 conference papers. Fred has been an Adjunct Professor of Electrical Engineering at Oregon State University, and is honored to be able to periodically teach circuit design courses as a Visiting Professor at the Johannes Kepler University in Linz, Austria.