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Welcome to the Phoenix Chapter of the IEEE Computer Society

Electronic System Level (ESL) Modeling and Methodologies

The field of Electronic System Level (ESL) continues to grow and build momentum, as the array of vendor offerings continues to grow in response to emerging industry standards and a widening variety of challenges.

With the establishment of the IEEE-1666 ESL Language Reference Manual (LRM), and the release of the TLM 2.0 (Transaction Level Modeling) Draft 2 by OSCI, the industry stands poised on the threshold of a new level of interoperability between vendor tools, third-party IP, and Customer’s needs.

The opportunities for application of ESL methodologies are many, ranging from architectural exploration to power estimation, software development, models and IP, early RTL verification, pre-silicon validation, higher-level synthesis, improved operability between abstraction levels, and more.

This talk will present a high-level overview and historical perspective on the evolution of System Level Design, including an introduction to SystemC and TLM. We will discuss some of the key challenges and opportunities facing the industry as it evolves to adopt and integrate ESL design methodology in order to manage increasing complexity, reduce costs, and shorten TTM (Time to Market) for today's products.

About the Speakers

Taylor Leaming

Taylor Leaming, an IEEE member since 1996, serves as a senior engineer in Intel's DEG Advanced Development Operations Group, where he is focused on development of ESL models, System Level Design tools, flows and methodologies, and Virtual Platforms. In addition to his development activities, he serves as chair for several ESL-related venues.

Prior to Intel, Taylor worked in Europe and the U.S. as a senior staff engineer at STMicroelectronics, where he and his team designed and introduced the world's first fully-integrated dual-mode USB/ISO Smartcard chip, authored numerous patents and publications, and developed a validation architecture for the Trusted Platform Module.

Earlier, he served in several roles as senior staff engineer and manager while at Motorola, where he was involved in the development of the 68060 and ColdFire microprocessors, and later in System-on-Chip design tools and methodologies.

Taylor began his career developing board-level designs for high-end real-time computer graphics systems used in aircraft simulators and other training, while working at Evans & Sutherland Computer Corporation.

He holds five patents related to USB and Smartcards, with ten others pending. His other interests include travel, personal computing and home improvement projects with his wife.

Zhu Zhou

Zhu Zhou has been working on various System Level Design methodologies/tools for more than ten years. As senior performance architect at Intel, Zhu Zhou develops standard-based transaction level modules for architectural exploration, defines and evaluates ESL design flows, and investigates power modeling methodology at the transaction level. Prior to Intel, he served as a staff principal engineer in Freescale Semiconductor’s Wireless and Mobile System Group, where he established high-level system design methodology using an internal SystemC-based tool for architectural exploration in terms of performance and power. Earlier, he spent more than six years as an applications engineer in the system level design group at Cadence Design Systems. He holds bachelor’s and master’s degrees in electrical engineering from Tong Ji University, Shanghai, PRC, and a Ph.D. in electronic engineering from Jiao Tong University, Shanghai, PRC.

Downloads

ESLOverview_IEEE-CSv1_2.pdf  (Presentation PDF)