Santa Clara Valley Circuits and System Society

IEEE SCV Circuits and Systems Society

Meetings Location	Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose, CA, 95134
Cadence San Jose Campus Map	Directions
Time: Free Parking	3rd Monday of the Month (usually) 6:30pm: Fast Food & drinks 7:00pm: Announcement 7:05pm: Presentation starts 8:15pm: Adjourn

Date: April 21. 2008
Title: Implementation of a Third Generation 16 Core 32 Thread Chip-Multithreading SPARC® Processor
Speaker: Georgios K. Konstadinidis

Date: May 19. 2008

IEEE CAS Distinguished Lecturer Program
Location: National Semiconductor Building E Auditorium 2900 Semiconductor Dr., Santa Clara, CA 95051
Directions
Co-sponsored by IEEE SCV SSC and MTT Chapters
Title: Achieving highly integrated, re-configurable RF front-ends in deep sub-micron
CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage
SAW filter in 90nm CMOS
Speaker: Naveen K. Yanduru

Date: Oct 20. 2008 (IEEE Distinguished Lecture)
Title: Multichip module packaging and its impact on architecture
Speaker: Hubert Harrer

Previous Events

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Charter

IEEE Santa Clara Valley Circuits and System Society focuses on the theory, analysis, design (computer aided design), and practical implementation of circuits, and the application of circuit theoretic techniques to systems and to signal processing. The coverage of this field includes the spectrum of activities from, and including, basic scientific theory to industrial applications.

Officers for 2008
Chair Navneet Jain Email: navneet at ieee.org	Vice Chair Mark Hooper Email:m.hooper at ieee.org
Program Chair Jonathan David Scintera Networks, Inc. Email: j.david at ieee.org	Treasurer Weikai Sun Email: swka at hotmail.com
Secretary Ping Chen Email: pingc@cadence.com	Publicity and Seminar Howard Sun Email: hjsun_1 at yahoo.com

Officers for 2008