Title: A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

Speaker:Jeff Sonntag (Synopsis)

Abstract:

Multi-Gigabit per second (Gbps) serial binary links are fast replacing traditional parallel data links in many applications. Examples include PCI moving towards PCIexpress and ATA moving towards SATA. Additionally, there exist many other applications with multi-Gbps serial links such as XAUI, FibreChannel and RapidIO. Thus the problem of architecting an effective Clock and Data Recovery (CDR) for multi-Gbps rates is becoming increasingly common. At the same time, the trend is for the serial link to become a peripheral function at the edge of a large ASIC, rather than the core function of a mixed signal ASSP. For this reason, effective solutions must be extremely low in power, implementable in the cheapest of digital process technologies, and easily ported across multiple technologies and speed targets.

In this paper we present and discuss a general architecture that meets these criteria. In section II, we present a small signal model and analysis for CDR's with bang-bang phase detectors. In section III, we describe and analyze the digital CDR. In section IV, we present measured results that corroborate the analysis of section III. Finally in section V, we summarize the results and describe the advantages of digital CDRs over analog implementations.