Abstract: Differential or Current-Mode Logic (CML) circuits are used in very high-speed applications where standard CMOS gates will not switch fast enough. Due to the size of this market, standard logic design and simulation tools have not been adapted to address this design niche, forcing designers to develop their own tools, or use custom (ie Analog) design tools and simulators. Using Analog simulator for this design space is very time-consuming, limiting the design size that can be worked on in a given timeframe, and usually preventing sufficient verification to be be completed prior to tapeout. Mixed signal simulators using Verilog-AMS netlists are able to address this design space, but examples are not widely available.
In this tutorial presentation Applications of CML logic are introduced, focusing on the Clock Divider for PLL's operating above 1-2GHz common in communication circuits. An overview of CML circuits and their operation is provided. Starting with a Verilog-A model of a basic gate, the development of a mixed signal model, and the required connect elements and rules are explained, and applied to the simulation of the clock divider. The presentation will close with the application of this circuit to the PLL and the resulting simulation performance improvements.