Abstract: Signal Integrity: Design, Test and Tolerance

With emergence of nanometer technology, signal integrity is becoming a major challenge to IC industry. With reduced noise margin and increased process variation, circuits become vulnerable to environmental interference and manufacturing defects. In modern designs like SoCs, there are millions of noise-prone nodes need to be analyzed, verified and tested. In this talk, we will briefly present following two topics:

1) Chip may fail to function due to design vulnerabilities, process variation or radiation effects. While it's expensive and difficult to achieve 100% accuracy in predicting compound noise effects, it is possible to efficiently analyze the aggregated noise impact on the overall robustness, identify the most vulnerable region of a design and subsequently guide repairing/optimization techniques.

2) Noise effects are sensitive to operational parameters such as power supply voltage, frequency and temperature, demanding at-speed testing for AC failures. Software-Based Self-Test (SBST) methodology, as an embedded test and validation solution, combines advantages of structural test and functional test. Not only can it test the circuit in a natural operational environment, it also provides an opportunity of cost-effective self-test and self-repair for SoC designs.