Abstract  
The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, as well as long test development and test application times. This talk will present test resource partitioning techniques that facilitate low-cost SOC test. Topics to be covered include the recent IEEE 1500 standard for testing core-based SOCs and techniques for modular testing of digital SOCs. Test planning methods that involve the use of wrappers and test access mechanisms will be discussed. Test scheduling techniques for the concurrent testing of embedded cores at the SOC level will also be presented. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test costs.