Abstract  
Current IC design trends calls for integration of power transistors within high-performance mixed-signal designs. Because of the increased power densities caused by such trends, temperature variations within the chip need to be taken into account to achieve cost-effective and reliable chip designs. This session will discuss the following: (1) Potential temperature hazards in IC designs and the need for electrothermal analysis; (2) The challenges of full-chip 3D temperature analysis of IC designs; (3) A temperature- aware methodology that uses detailed temperature information for design improvements of mixed-signal chip designs; (4) An effective temperature- aware design flow at AMIS using Cadence Spectre electrical circuit simulation and thermal analysis tools from Gradient Design Automation. AMIS and Gradient collaborated on a thermal analysis project that allows detailed 3D full-chip temperature distribution within the chip to be calculated and visualized early in the design cycle before taping out. Such temperature checking capability is useful for predicting potential temperature hazards under steady state and transient temperature conditions. Traditional methods of temperature estimates based on power and package parameters do not provide sufficient details while commercial mathematical software tools lack the accuracy needed in contemporary chip-level designs. Using layout and netlist data available in the Cadence design environment, an automated flow has been developed that annotates instance-specific temperatures to Spectre simulation to obtain true temperature- aware power from it. The resulting temperature information is used for floorplanning to reduce design guardbands and potential circuit malfunctions.