Abstract  
The multicarrier transceiver has found applications in a wide range of wired or wireless transmission channels. It is typically called DMT (discrete multitone) for wired DSL (digital subscriber loops) applications such as ADSL (asymmetric DSL) and VDSL (very high-speed DSL), and called OFDM (orthogonal frequency division multiplexing) for wireless LAN (local area network) and broadcasting applications such as digital audio broadcasting and digital video broadcasting. For wireless transmission, the channel profile is usually not available to the transmitter. The transmitter is typically channel independent and there is no bit/power allocation. Moreover having a channel independent transmitter is of vital importance for broadcasting applications, where there are many receivers with different transmission paths. In wired DSL applications, the channel does not vary rapidly. This allows the receiver to send channel profile back to the transmitter through a reverse channel. In this lecture, we consider optimal transceiver design for two cases: (i) channel profile available at the transmitter; (ii) channel profile not available at the transmitter. In the first case, the transmitter is channel independent and the channel dependent part of the transceiver should be only at the receiver. The optimal transceiver that minimizes bit error rate rate subject to the same transmission power will be designed. For the second case, bit and power allocation can be used to exploit the disparity among the subchannel noise variances. The optimal transceiver that minimizes transmission power subject to the same transmission bit rate and the same bit error rate will be derived. Substantial gain can be achieved using the optimal transceiver, especially for moderate number of subcarriers. The popularity of system-on-chip (SOC) integrated circuits has led to an unprecedented increase in test costs. This increase can be attributed to the difficulty of test access to embedded cores, as well as long test development and test application times. This talk will present test resource partitioning techniques that facilitate low-cost SOC test. Topics to be covered include the recent IEEE 1500 standard for testing core-based SOCs and techniques for modular testing of digital SOCs. Test planning methods that involve the use of wrappers and test access mechanisms will be discussed. Test scheduling techniques for the concurrent testing of embedded cores at the SOC level will also be presented. Together, these techniques offer SOC integrators with the necessary means to manage test complexity and reduce test costs.