Vassilios Gerousis Biography:

Vassilios is currently working at Cadence as a senior architect in the digital IC division. He spent 6 years working at Infineon technology In Germany working on advanced design methodology to address challenges in 90 NM and 65 NM silicon technologies. He helped to pioneer low power support in support of 90 NM developments, then he focused on yield-aware design methodology to address 65 nm silicon challenges. He spent 18 years working for Motorola Semiconductor, mostly in advanced design methodology. The work he has done at both Infineon and Motorola, helped to drive commercial EDA support to support next generation silicon process. After graduation with doctorate degree in electrical Engineering from Northeastern University he spent three years at TI working in their ASIC bipolar group. Vassilios Gerousis has been active in industry standards and his latest success is SystemVerilog standardization and industry adoption.