Upcoming IEEE SCV EDS Evening Meeting:
June 13, 2006 IEEE SCV EDS Meeting:
"CMOS Device Reliability Overview"
Speaker: Dr. Sunil Shabde - Silicon Analytics
Subject: "CMOS Device Reliability Overview"
Location: National Semiconductor, Building 31 Large Auditorium,
955 Kifer Road, Sunnyvale, CA.
See the meeting location map
Time: 6:00 PM - Pizza , 6:15 PM - Lecture
Speaker Contact:
Jayasimha Prasad
Abstract:
Dr. Sunil Shabde will give a talk on CMOS device
reliability, with emphasis on the current and
emerging degradation mechanisms.
With continuous scaling down of the CMOS technology,
several device reliability issues have arisen, such as
hot carrier degradation (HCI), gate oxide reliability
issues (TDDB, QBD) and electro-migration (EM).
This talk will present an overview of the degradation
phenomena, the underlying physics, commonly used models
and lifetime evaluation methodologies, with a focus
on device issues.
As the technology scales further below 0.18 microns,
band-to-band tunneling becomes significant due to
thinning of the gate oxides. Gate leakage increases
exponentially and becomes detrimental to products.
New reliability issues such as NBTI, PBTI, TDDB and
the soft breakdown of ultra thin-oxides arise. Impact
of Hi–K gate dielectrics on reliability also becomes
a significant issue.
An overview of these emerging reliability effects will
be given and the physics behind them will be explained.
Interestingly, it will be briefly pointed out that with
continued scaling there is a certain continuity as well
as a merging of some of these degradation mechanisms.
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Upcoming IEEE SCV EDS Evening Meeting:
Biography:
Sunil Shabde holds a PhD in Electrical Engineering
from Rice University, an MSEE from Purdue University,
and the BE from the Indian Institute of Science,
Bangalore.
He has over 25 years of experience as a senior
technologist and manager in companies ranging from
start-ups to large corporations.
His contributions are in CMOS technology development
including process development, device physics, yield
improvement, process qualification and reliability
issues. At AMD, Signetics/Philips and AMI he worked
on process integration, device characterization and
process transfers.
His experience also includes managing foundry interfaces
at companies such as QSI, Amkor and high-voltage device
development at IMP. At AMD, he did CMOS device reliability
evaluations for qualifying an 0.25 micron logic technology.
He was granted three patents while at AMD.
Dr. Shabde has former academic experience as a faculty
member at the University of Michigan, Ann Arbor where he
set up an integrated circuits laboratory. He has also
taught evening courses on CMOS technology and wafer level
reliability at the UC Extension, Santa Cruz.
He has published 16 papers in the area of device physics
and reliability issues in various technical journals such
as the IEEE Transactions on Electron Devices (TED) and at
the IEEE International Reliability Physics Symposium (IRPS).
Dr. Shabde is a Senior Member of the IEEE.
Dr. Shabde currently consults with Silicon Analytics and
delivers courses on Wafer Level Reliability for Pinnacle
Training International Seminars, Inc. He has recently
delivered his course on Wafer Level Reliability on-site
at companies like Texas Instruments (TI).
For more information on his
Wafer Level Reliability Course
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