2017 Meetings

The linked titles of some meetings are the presentations speakers provided.

September 12, 2017: "Framework for Automated PCB Material Characterization " Jayaprakash Balachandran and Ching-Chao Huang

Abstract: As SERDES data rates move past 25 Gbps to 50 Gbps and beyond, PCB channels have become limiter for SERDES Link Performance. As a result, PCB Channels needs to be well characterized and the dielectric materials must be carefully chosen to optimize the cost and performance. However, there are so many options for constructing PCB stack up such as copper surface roughness, trace width and thickness dielectric material choices and weave types. This makes characterization overwhelming and challenging. In this talk, we will discuss an automated framework for PCB Material characterization. The framework helps to quickly de-embed PCB traces and extract PCB material properties for hundreds of VNA measurement files. We will also briefly touch upon the concepts of causal de-embedding and IEEE P370 efforts in standardizing interconnect characterization.

Jayaprakash Balachandran

Bio: Jayaprakash Balachandran (JP) is with Unified Compute Server (UCS) Group at Cisco Systems Inc. JP hasover 15 years of experience in high speed design and has a PhD in High Speed Interconnects from IMEC Belgium. He has many peer reviewed publications and has been an invited speaker in conferences. A paper he co-authored won Designcon 2017 Best Paper Award.

Ching-Chao Huang

Bio: Ching-Chao Huang, founder and president of AtaiTec Corporation, has more than 30 years of high-speed design and SI software development experience. He was advisory engineer at IBM, R&D manager at TMA, SI manager at Rambus, and Sr. VP at Optimal. Dr. Huang is an IEEE senior member and he pioneered In-Situ De-embedding (ISD) for causal and accurate de-embedding. He received his BSEE from National Taiwan University and MSEE and PhD from Ohio State University.

June 13, 2017: " Identifying, visualizing and minimizing EMC and EMI problems using 3D EM simulation " David Johns

Abstract: In today’s high tech world, companies are under tremendous pressure to innovate and bring new products to market with minimal delay. At the same time, electronics products are getting more challenging to design due to higher data rates, higher component densities, reduced physical space and demands for conformal/flexible structures. Designers and analysts often face competing design requirements, such as EMC and thermal conflicts. On a positive note, computational electromagnetic methods have evolved significantly over the last few decades and combined with incredible improvements in computing speed and capacity, electromagnetic simulation has become an integral and important part of the design process. This presentation will discuss the state of the art in EMC simulation and provide examples of identifying, visualizing and minimizing EMC problems.

David Johns

Bio: David Johns is currently the VP of Engineering for CST of America, responsible for CST’s technical support and engineering services in North America. He completed his PhD at Nottingham University in the UK in 1996 for his research work on the 3D TLM method for electromagnetic field simulation. David has over 25 years of experience in developing and applying computational electromagnetics to a wide range of applications including EMC, EMI, ESD, E3 and MW/RF and Antennas. He is a frequent speaker at the IEEE International EMC symposium and has authored many papers and articles on the subject of EM simulation.

May 09, 2017: " Rest-of-World Compliance for Wireless Products " Mark Maynard

Abstract: Obtaining international product compliance approvals for electrical and electronic devices is a key goal for manufacturers and developers wanting to get their products to an ever-larger market of potential customers. This need is growing with the expansion of governmental wireless/telecom regulatory requirements that are required for most modern electronic devices in this age of the "Internet of Things", or IoT. While much has been written on launching your products into the largest market countries in North America, the European Union, and the Asia-Pacific economic powerhouses of China, India, Japan, South Korea, Australia, and Taiwan, there has not been much published on the next secondary markets that should be accessed. Identifying these "next step" countries and their associated governmental telecom agencies is the focus of this presentation, along with exploring different metrics for evaluating if these potential markets make sense for your products.

Mark Maynard

Bio: Mark is the Business Development and Communications Manager at American Certification Body, Inc. He is an IEEE Senior Member, an active committee member for the annual IEEE Electromagnetic Compatibility (EMC) Society Symposium since 2013, and a past-president of the IEEE Product Safety Engineering Society. He has spent over 25 years working in the Regulatory Compliance Engineering field for ITE and electronics, covering international product approvals for EMC/EMI, Wireless/Telecom, Product Safety, and Design for the Environment. Mark is a frequent contributor to In Compliance magazine, and conducting compliance engineering training has been one of his key job functions since 2013. He has two degrees from Texas State University, one in Mathematics, and the other in Business & Marketing.

April 11, 2017: " Statistical Process Control (SPC) for an EMC Laboratory " Kimball Williams

Abstract: Measurement system variability in a test laboratory can be a source of discomfort for the test engineer, the designer and management. This is especially true in product development laboratories where the question of exactly what effect a design change had on system behavior is of central interest. The use of Statistical Process Control (SPC) methods to gage and track the variability of system measurements can provide confidence in the repeatability of the system setup, and in the data it produces. However, the use of SPC in an EMC Lab, especially for frequency domain measurements, requires decisions to limit the quantity of the data to avoid information overload. To accomplish this careful selection of the measurement methods is essential.

Bio: Kimball Williams completed his career and retired from DENSO as a " Technical Fellow " in 2012 after managing its EMC Test Laboratory. He is an iNARTE certified Master EMC Design Engineer, EMC Test Engineer and ESD Test Engineer with Lifetime certification from iNARTE. Kim is also an IEEE Senior Life Member and Past Chair of the IEEE Southeastern Michigan Section and an ' Honored Member ' of the IEEE EMC Society where he serves as one of the Past Presidents Emeritus and current Director of Professional Activities. Kim is a licensed private pilot, PADDY certified scuba diver, licensed amateur radio operator (Call sign: N8FNC) and plays classical guitar in his ' spare ' time.

February 14, 2017: " Effective, Small, and Inexpensive Common-Mode EMI Reduction Using Inverse Secondary Current Cancellation " Randall Elliott

Abstract: This presentation is about implementation of a small, cheap and highly effective (10-20dB) EMI reduction method attacking the 150kHz to 3MHz range of Conducted EMI from the most notorious source. It is particularly effective where 2-wire AC input (no AC ground) is used, if 50-60Hz output leakage current is an issue, or improvement to space, cost and efficiency is desired. It reduces or eliminates traditional brute-force filtering, transformer shielding and other "conventional" methods.

Bio: Over 40 years in electronics from a USFS Comm Tech Assistant in 1973. Recruited by Tektronix from Idaho State University in 1978, Randy has explored many positions in Portland-area high-tech companies often involving unusual analog and power designs with EMI suppression. These include: Motor Drivers at Synektron, Industrial Control Systems at Precision Interconnect, Optical Spectrum Analyzer at Photon Kinetics, CCD Camera Systems at SiTE/PixelVision, Power Supply FAE for Delta Electronics (Taiwan), Fitness Equipment with Nautilus, Lighting Controls for Leviton, Energy Meters at Veris/Schneider, assorted side jobs through Randoid LLC.Licensed Professional Engineer since 1999 and Amateur Radio Extra Class since 2006. President of Tigard CERT Amateur Radio Group. Pursuits into renewable energy, water treatment and Ham Radio antenna and balun projects. Randy is an IEEE Senior Member of the Power Electronics, EMC, Product Safety, Circuits and Systems, Antennas and Propagation, and Magnetics Societies.

January 10, 2017: " Emission Source Microscopy and related near field scanning methods " David Pommerenke, Electromagnetic Compatibility Laboratory at Missouri University of S&T

Abstract: Near field scanning visualizes the fields close to a product, e.g., an IC or PCB. However, it misleads us often by letting us associate areas of strong near field with causes of far field radiation. For example, if a microstrip trace is scanned it will show strong near fields over the trace. However, these fields do not radiate! Only the beginning and end of the microstrip cause the radiation. Emissions source microscopy allows to only visualize the radiating fields, any none radiating fields will not be shown. This sounds great, but it comes at a price: The resolution of near field scanning is determined by the probe size, and the probe to source structure distance. Thus, it can achieve 0.5mm or better. Emissions source microscopy has the same limitations as optical microscopy: The resolution is about lambda/2. Good at 30GHz, not really useful on a PCB at 500MHz. The talk will introduce the emissions source microscopy, show how limitations can be partially overcome, show that the total radiated power can rather easily be determined and illustrate by example that a complete scan can be performed in 10min. The method allows numerical " what if " experiments, by masking radiating areas one can quantify how large the contribution of each area is. Examples will be shown and other scanning techniques, such as ESD susceptibility scanning will be discussed.

David Pommerenke

Bio: David Pommerenke ' s research interests are system level ESD, electronics, numerical simulations, EMC measurement methods and instrumentations. He received the Ph.D. from the Technical University Berlin, Germany in 1996. After working at Hewlett Packard for 5 years he joined the Electromagnetic Compatibility Laboratory at the Missouri University of S&T in 2001 where he is professor . He is IEEE fellow and associated editor for the IEEE Transactions on EMC and published > 200 papers on areas ranging from high voltage to numerical methods with the main emphasis on measurement methods and ESD.