About SFBAC-PELS
The San Francisco Bay Area chapter of the IEEE Power Electronics Society (IEEE SFBAC-PELS) is interested in the development of power electronics technology. This technology encompasses the effective use of electronic components, the application of circuit theory and design techniques, and the development of analytical tools toward efficient electronic conversion, control, and conditioning of electric power.

SFBAC PELS is the winner of three awards in 2017: PELS Best Chapter, Region 6 Outstanding Chapter, and SCV Section Outstanding Chapter.



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Power Integrity Half-Day Workshop
San Francisco Bay Area PELS Chapter

Speaker:
Steve Sandler, Founder and CTO of Picotest.com

Thursday, May 17, 2018
1:00pm - 5:00pm: Workshop Session including light snacks/drinks

Texas Instruments
Building E Conference Center
2900 Semiconductor Blvd.
Santa Clara, CA 95051

Registration Required!

Admission: $40 PELS members, $45 IEEE Members, $55 Non-IEEE.
Students and TI'ers: Free (limit 10 people)

Walk-In Registration: $65

Thank you to our sponsors:


Rohde & Schwarz

Picotest
Special thanks to Venue Sponsor Texas Instruments

Workshop Abstract:

Power Integrity (PI) is driving design performance. Many hi-reliability industries have focused on the PI ecosystem and its impact on high performance circuit designs, though awareness of PI issues and its ramifications have still not reached the majority of design engineers. With each new generation of high speed digital and RF circuitry, your designs are expected to perform at higher frequencies while the supply voltages are being reduced to meet new power efficiency goals. As the result, circuits have become increasingly sensitive to power supply noise and PDN impedance mismatches. As voltage margins have decreased, even minor variations in the supply voltage interacting with your PCB design have large detrimental impacts on system performance.

This talk will focus on testing, simulating, and optimizing your power supply, power delivery network (PDN), and their integral components, for successful power integrity design.

Agenda:

  • Lecture:
    • o Introduction to Power Integrity
    • The Power Supply and its Relationship to Target Impedance
    • Flat Impedance and Decoupling Design
    • Simulation and Modeling for PI
  • Demonstrations:
    • Non-Invasive Stability Measurement (NISM)
    • Differences Between 1- and 2-port Measurements: Components & Circuits
    • The PDN Measurements: 2-port Shunt Thru Impedance Measurement

About the Speaker:

Steve Sandler has been involved with power system engineering for nearly 40 years. Steve is the founder and CTO of PICOTEST.com, a company specializing in instruments and accessories for high performance power system and distributed system testing. Steve is also the founder of AEi Systems, a company specialized in worst case circuit analysis for high reliability industries.

He frequently lectures and leads workshops internationally on the topics of Power Integrity and Distributed Power System Design. He is a Keysight Certified EDA expert. Steve is also a recent Winner of the Jim Williams ACE Award for Contributor of the Year (2015) and a 2-time Test & Measurement Test Engineer of the Year Finalist.

Steve publishes articles and books related to power supply and power distribution network performance and power systems modeling. His latest book, Power Integrity: Measuring, Optimizing and Troubleshooting Power-Related Parameters in Electronics Systems was published by McGraw-Hill in 2014. Most recently he was the recipient of both the DesignCon 2017 and EDICON 2017 Best Paper Awards.


Congratulations to the SFBAC-PELS Chapter!

2017 Worldwide PELS Best Chapter Award

2017 Region 6 Outstanding Chapter

2017 SCV Section Outstanding Chapter