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IEEE SCV Signal Processing Society

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Meetings: Usually second Monday of the month (except for July and August)

Location: National Semiconductor (north end of Building E - see map1 & map2, 2900 Semiconductor Dr., Santa Clara, CA 95051  (Near the intersection of Lawrence and Central Expressway);

Directions: Take 101 to Lawrence Expressway. Head south on Lawrence to Kifer (past Central). Turn right on Kifer. Turn right on Semiconductor Dr. and drive all the way back to north end to Buldg E.  Entrance is on the West side of the building.

Free Parking: National Semiconductor parking lot. 


Time: 
6:30pm: Fast Food & drinks ($2 Donation Recommended towards Refreshments)

7:00pm: Announcements
7:05pm: Talks starts
8:15pm: Adjourn


Subscribe to Announcements:  
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Future meetings and seminars:

(Co-sponsored seminar with SCV CAS, CPMT and CS chapters)

Date:  Oct 20, 2008

Time:  Dinner from 6:30pm to 7:30pm; talk starts at 7:30pm ***Note not at regular meeting site, date and time***

Title: Multichip module packaging and its impact on architecture

Speaker: Dr. Hubert Harrer, Senior Technical Staff Member, Server and Technology Group, IBM

Location: Ramada Inn in Sunnyvale (Click here for map and directions)

 

(Note: This meeting is not be held at the regular SPS meeting location. It also includes a dinner from 6:30pm to 7:30pm. To reserve your spot for dinner please visit IEEE SCV CPMT website. Seminar is free of charge.)

Abstract:
The presentation compares the system packaging and technologies of IBM´s latest system z high end servers.

Starting from the z900, the system design change towards a blade-like architecture will be explained. The latest system generation z9 has achieved a doubling of the multiprocessor performance compared to the z990 system by maximizing its CPU configuration in combination with increasing the speed of the interconnections.

This MCM technology is the key enabler for the high bandwidths between processor chips and the cache chips. The glass ceramic module has accomplished this challenge within the 102 layers resulting in a total wiring length of 545m. The increase of bandwidth requirements for the packaging will be compared for the last generations. Also the complex board and card technology of the second level packaging will be discussed. The cooling of the system is being done with a modular refrigeration unit (MRU), which cools the processor chips down to 45C. This low temperature ensures highest reliability and reduced leakage current of the chips. An air cooled backup mode at a lower frequency ensures that the system does not go down in case of an MRU fail. The MCM has been designed for a maximum power of 850W during nominal operation and 1200W in case of the air-cooled backup mode.

The presentation will focus on the electrical design methodologies for high end servers like power delivery concepts, signal integrity methodologies and power integrity designs for delivering such high currents.

Biography:

Dr. Hubert Harrer is a Senior Technical Staff Member (STSM) since 2002 working in the IBM Server and Technology Group. He received his Dipl.-Ing. degree in 1989 and his Ph.D. degree in 1992 from the Technical University of Munich. In 1993 he received a DFG research grant to work at the University of California at Berkeley in the paradigm of Cellular Neural Networks. Since 1994 he has worked for IBM in the Boeblingen Packaging Department. In 1999 he was on international assignment at IBM Poughkeepsie, New York. He was leading the z900 MCM designs and is the technical lead for z-series CEC packaging designs since 2001. This includes the system z990 and system z9 mainframe computers. His technical interests focus on packaging technology, high frequency designs and electrical analysis for first and second level packaging. He has published multiple papers and holds 7 patents in the area of packaging.


(Co-sponsored Distinguished Lecture with SCV CAS and MTT chapters)

Date:  Nov 3, 2008 (Note: This meeting is not be held at the regular SPS meeting location.)

Title: Design Techniques and CMOS Implementation of Low Noise Amplifier (LNA)

Speaker: Prof S. S. Jamuar

Location: (Tentatively) QUALCOMM facility at 3165 Kifer, in Santa Clara, 95051 between Bowers and Corvin

 

Abstract:
The rapid growth of portable RF communication systems in various standards has led to the demand for one chip to cover several standards such as WCDMA, WLAN, GSM etc. This leads to the stringent requirements for the RF front-end to cover a large range of different carrier frequencies for all standards. A receiver system consists of the following circuits: a low noise amplifier, mixer, voltage-controlled oscillator (VCO), intermediate frequency (IF) amplifier and filters. The low noise amplifier (LNA) is typically the first active stage for the RF front-end. Its main function is to amplify low signals without adding noise, thus preserving the signal-to-noise ratio (SNR) of the system at low power consumption. Many tradeoffs are involved in designing the LNA such as noise figure (NF), linearity, gain, impedance matching and power dissipation. Therefore, proper LNA design considerations and techniques are crucial in today’s communications technology.

This lecture places an emphasis on improved design techniques for the low noise amplifier (LNA). DC biasing techniques, impedance matching techniques, noise matching and stability analysis will be discussed. Voltage mode design and current mode design techniques will be elaborated. Variable gain low noise amplifier design techniques will also be discussed. All the design techniques and simulations presented in the tutorial will be based on EDA tools.

Biography:

Prof. S. S. Jamuar received his M. Tech and Ph. D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975-76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined as Lecturer Electrical Engineering Department at Indian Institute of Technology Delhi in 1977, where he became Assistant Professor in 1980. He was attached to Bath College of Further Education, Bath (UK), Aalborg University, Aalborg (Denmark) during 1987 and 2000. He was a Professor in the Department of Electrical Engineering at IIT Delhi from 1991 to 2003. He was Consultant to UNESCO during 1996 in Lagos State University, Lagos (Nigeria). He was with University Putra Malaysia during 1996-97 in the Faculty of Engineering. Presently he is Professor in the Electrical and Electronic Engineering Department in the Faculty of Engineering, University Putra Malaysia (Malaysia) since 2001. He has been teaching and conducting research in the areas of Electronic Circuit Design, Instrumentation and Communication Systems. He has about 40 papers in the International Journals and has attended several International Conferences and presented papers. He recently received Taiwan Patent on Simulation Circuit Layout Design for Low Voltage, Low Power and High Performance Type II Current Conveyor. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, . Distinguished Alumni Award from BIT Sindri in 1999, Best paper award in IETE journal of Education 2004 from IETE. He is senior member of IEEE and Fellow of Institution of Electronics and Telecommunications Engineering (India). He is on the Editorial Board of Wireless Personnel Communication Journal. He is presently the Chapter Chair for IEEE CAS Chapter in Malaysia. He is one of DLP speakers for the term 2008-2009 for the IEEE Circuits and System Society.


 

Past Events and Meeting Abstracts and Slides

Sep 22, 2008: Past and Future of Digital Watermarking

Aug 30, 2008: SPS SCV Workshop on Bio-informatics and Bio-signal Processing

June 2, 2008: Enhancing Image Fidelity through Spatio-Spectral Design for Color Image Acquisition, Reconstruction, and Display

May 12, 2008: Content-Adaptive Efficient Resource Allocation for Packet-Based Video Transmission

Apr 14, 2008: RF Systems Design :Fundamental Theory and WiMAX Examples

Mar 10, 2008: Digital Fingerprinting for Multimedia Forensics

Feb 11, 2008: Simplified Fast Motion Estimation: Simplified and Unified Multi-Hexagon Search (SUMH) with Context Adaptive Lagrange Multiplier (CALM)

Jan 7, 2008: An Open Baseband Processing Architecture for Future Mobile Terminal Design

Dec 10, 2007: Re-Live the Movie "The Matrix": From Harry Nyquist to Image-Based Rendering

Nov 12, 2007: Efficient Techniques for MPEG-2 to H.264 VideoTranscoding

Oct 8, 2007: Overview of Multimedia Signal Processing on Multi-Core Processors

Sep 17, 2007: Transceiver Designs for Multicarrier Transmission

Sep 10, 2007: Overview of WiMax Technology and Evolution {Slides}

May, 2007: Tesla Roadster: Embedded microprocessors and Design trade-offs!

March, 2007: A Simulation Model for IEEE 802.11n

Feb 12, 2007: A/D and D/A Converters with Integrated High-speed Compression

May 12, 2006: New Directions in Home Theater Systems

Apr 10, 2006: Correcting Distortion in Multi-media Audio Terminals

Feb 13, 2006: Distributed Wireless Communication: A Shannon-Theoretic Perspective on Fading Multihop Networks {Slides}

Dec 12, 2005: Mobile WiMAX: True Broadband Wireless Enabled {Slides}

Jun 13, 2005: Using Technology to Keep Other Countries Honest 

Apr 25, 2005: How many antennas does it take to get broadband wireless access? - The story of MIMO {Slides}

Jan 10, 2005: Converting MATLAB Algorithms to FPGA or ASIC Designs

Dec 13, 2004: Reconfigurable Systems Emerge {Slides}

Nov 08, 2004: Nonlinear adaptive systems

Sept 13, 2004: Anytime, Anywhere IP Communications

June 14, 2004: Fortran 95, or Matlab meets C++

April 12, 2004:On the Deployment of the Voice Biometric: Challenges and Best Practices

March 08, 2004: Telephony Speech Recognition Application Testing {Slides}

Feb 05, 2004:Speech Technology for Computer Assisted Language Learning (CALL) {Slides}

 


Charter

IEEE Santa Clara Valley Signal Processing Society focuses on all aspects of the theory and application of Signals involving filtering, coding, transmitting, estimating, detecting, analyzing, recognizing, synthesizing, recording, and reproducing signals. The term "signal" includes audio, video, speech, image, communication, geophysical, sonar, radar, medical, musical etc.

 

2007 Officers 

 Chair

 Tokunbo Ogunfunmi

tokunbo[at]ieee[dot]org

 

Vice Chair

 

Xiaoshu Qian

xiaoshu[dot]qian[at]intel[dot]com

Treasurer

Vlad Potanin

vlad[dot]potanin[at]nsc[dot]com

Secretary

Douglas Chan

douglas[dot]chan[at]ieee[dot]org

 

Program Coordinator

Yen-Kuang Chen

y[dot]k[dot]chen[at]ieee[dot]org

 

 

Photos from past meetings 

URL:
http://www.ewh.ieee.org/r6/scv/sps 

2006 Officers

Chairman
M Saseetharran

Vice Chairman/ Treasurer
Man Po (Bill) Lam

Program Co-ordinator
Brian Sublett

Treasurer
Ozur Oyman

Secretary
Madan Ankapura

 

2005 Officers

Chairman
M Saseetharran

Vice Chairman/ Treasurer
Man Po (Bill) Lam

Program Co-ordinator
Brian Sublett

Secretary
Vikash Rungta

Just Joined
Madan Ankapura

 

2004 Officers

Chairman
M Saseetharran

Vice Chairman
P S Chang

Secretary
Nelson Zierbach

Treasurer
V (Ramki) Ramakrishna

Auxiliary Officer
Kenneth White

 

 

 

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(Last modified: Oct 9, 2008)