IEEE Signal Processing Society, Santa Clara Valley Chapter

Workshop on FPGAs for Digital Signal Processing Applications

Location: Bannan Engineering Laboratories, School of Engineering, Santa Clara University

Date: Saturday, Feb. 7, 2009

Time: 8:00am – 5:00pm

Topics at a glance

(1) Why and when to use DSPs, FPGAs and ASICs

Speaker: Dr. Xiaoshu Qian, Intel Corporation

(2) FPGA Architectures for H.264 Video Processing

Speaker: Prof. Tokunbo Ogunfunmi, Santa Clara University

(3) FPGAs: Re-inventing the Signal Processor and MIMO-OFDM Applications

Speaker: Dr. Chris Dick, Xilinx Corporation

(4) FPGA-Based Embedded Wideband Audio Codec System

Speaker: Prof. Chang Choo, San Jose State University

(5) A Platform-Based Approach to Realizing High-Performance DSP Subsystems in FPGAs

Speaker: Dr. Jim Hwang, Xilinx Corporation

Workshop Website

http://ewh.ieee.org/r6/scv/sps/fpgaSPS/

Workshop Flyer

http://ewh.ieee.org/r6/scv/sps/fpgaSPS/flyer.pdf

Tentative Agenda

8:00 am - 8:30 am	Registration/breakfast
8:30 am - 8:45 am	Welcome address/introduction
8:45 am - 9:15 am	Topic 1: Why and when to use DSPs, FPGAs and ASICs
9:15 am - 9:20 am	Break
9:20 am - 10:50 am	Topic 2: FPGA Architectures for H.264 Video Processing
10:50 am - 11:00 am	Break
11:00 am - 12:30 pm	Topic 3: Re-inventing the Signal Processor and MIMO-OFDM Applications
12:30 pm - 1:30 pm	Lunch
1:30 pm - 3:00 pm	Topic 4: FPGA-Based Embedded Wideband Audio Codec System
3:00 pm – 3:10 pm	Break
3:10 pm - 4:40 pm	Topic 5: A Platform-Based Approach to Realizing High-Performance DSP Subsystems in FPGAs
4:40 pm - 5:00 pm	Q&A, wrap-up panel discussion: Engineering Challenges and Business Opportunities

Detailed Workshop Program

http://ewh.ieee.org/r6/scv/sps/fpgaSPS/program.html

Directions to Bannan Engineering Laboratories in Santa Clara University and Parking information

Directions, parking information and map to workshop location: http://ewh.ieee.org/r6/scv/sps/fpgaSPS/map.html

Bannan Engineering Laboratories on Santa Clara University campus

Registration

	Before Feb 1 (extended!)	After Feb 1 or on-site
IEEE member	$70	$80
Non-IEEE member	$80	$90
Student	$30	$40

Registration includes a copy of the workshop proceedings, lunch, breakfast and coffee.

Follow this link to register: http://ewh.ieee.org/r6/scv/sps/fpgaSPS/register.html

Contacting the Workshop

• SPS SCV Chair: Tokunbo Ogunfunmi, email: tokunbo[at]ieee[dot]org
• SPS SCV Program Coordinator: Yen-Kuang Chen, email: y[dot]k[dot]chen[at]ieee[dot]org
• Chapter Website: http://ewh.ieee.org/r6/scv/sps/

__________

Website revision history:

Jan 5, 2009

- First post of workshop website.

Jan 8, 2009

- Corrected typo in detailed program page.

Jan 14, 2009

- Online registration opens!

Jan 27, 2009

- Early bird discount extended!

Feb 2, 2009

- Early bird discount ended.

Website last modified: Feb 2, 2009