IEEE Signal Processing Society, Santa Clara Valley Chapter
Workshop on FPGAs for
Digital Signal Processing Applications
Location: Bannan Engineering
Laboratories,
Date: Saturday, Feb. 7, 2009
Time: 8:00am – 5:00pm
Workshop Program
1. Why and when to use
DSPs, FPGAs and ASICs
Speaker: Dr.
Xiaoshu Qian, Intel Corporation
Abstract:
We will provide a brief
up-to-date comparison of Digital Signal Processors (DSPs), Field-Programmable
Gate Arrays (FPGAs), and Application Specific ICs (ASICs) to set the stage for
subsequent presentations on using FPGAs for digital signal processing. We will
compare these technologies in terms of the programmability, speed, power
consumptions and cost, and highlight the major progresses in the last few
years.
2. FPGA Architectures
for H.264 Video Processing
Speaker: Prof. Tokunbo Ogunfunmi,
Director, Signal Processing Research Lab. (SPRL), Dept. of Electrical
Engineering,
http://www.scu.edu/engineering/ee/people/ogunfunmi.cfm
Abstract:
H.264/AVC
is a very important standard in video compression/transmission area because of
its high coding efficiency and robustness. H.264 is an ITU video standard
used in many scalable video applications. In this talk, we review the basics of
H.264 and more recent standards, then we cover
hardware architectures for processing major parts of the standard. These
include motion estimation, and transform and quantization. We focus on architectures that are
configurable and implementable on FPGAs such as the Xilinx FPGA. We present two
examples: A new
hardware architecture for 8x8 integer
transform and quantization for H.264 which promises minimal resource
utilization. In the architecture, each pixel is processed one by one on a
simplified pipeline without multiplication. Thus, redundant modules, which are
used for block-based or row-based parallel processing, can be reduced. Experimental results show that it can reduce
resource 30% compared to previously proposed models. It covers wide ranges of
parameters as well. A hybrid fast
motion estimation algorithm – Simplified Unified Mult-Hexagon (SUMH) search
(also known as the Simplified Fast Motion Estimation (SFME) algorithm), is a
non-normative part of the H.264/AVC standard. We have made hardware-oriented
modifications to SUMH and implemented a configurable,
pipelined hardware architecture for the modified SUMH. The architecture is
prototyped using Digilent XUP V2P board which contains a Virtex-II Pro XC2VP30
Xilinx FPGA and is capable of processing
CIF frame sequences in real-time.
3. FPGAs:
Re-Inventing the Signal Processor and MIMO-OFDM Applications
Speaker:
Abstract:
As semiconductors become
more complex and new milestones in transistor size and performance are
achieved, power consumption and thermal management have emerged as limiting
factors to the continued pace of chip design and manufacturing of high-performance
devices. Moving to the era of multi-billion transistor chips, device technology
evolution along the same axis is not sustainable, because we would be looking
to build devices that run as hot as a rocket engine exhaust nozzle. The
solution is commercial deployment of concurrent processing.
While parallel processing
for DSP has roots going back several decades, its promise of high-performance
has not really been delivered until recently. The delivery vehicle is the field
programmable gate array (FPGA). While early attempts to commercialize parallel
DSP failed, the technology context is now right for providing high-performance
signal processing platforms based on concurrent computing concepts. The
presentation provides an overview of FPGA signal processing and contrasts the
FPGA DSP with other technologies that are employed for solving real-time signal
processing problems.
MIMO-OFDM is a cornerstone
technology for many key wireless communication systems and many of the key signal processing tasks performed in these systems require
significant arithmetic resourcing. Further, it is often desirable to maintain
an element of flexibility in these systems in order to extend network
functionality with new signal processing capabilities once the system is deployed,
or to allow the one hardware platform to support multiple air interfaces. The
joint requirement of flexibility and high-performance is one of the reasons
that make this application space well suited to realization using FPGAs. This
presentation will provide an overview of the architecture and FPGA
implementation of a MIMO-OFDM communication system using a Simulink® -based
tool chain called System Generator for
DSP. Moving forward, one of the key requirements of virtually all wireless
systems will be increased data capacity. For OFDM modulation, one of the
natural methods for delivering increased data rates is spatial multiplexing
(SM) MIMO. There are significant computational challenges to the realization of
maximum likelihood (ML), or quasi-ML, SM MIMO decoders. The presentation
provides an overview of the FPGA realization of a sphere detector for SM MIMO
waveforms. The architecture and micro-architecture design considerations for producing efficient
FPGA implementations of these decoders are examined.
4. FPGA-Based Embedded
Wideband Audio Codec System
Speaker: Prof.
Chang Choo,
http://www.engr.sjsu.edu/choo/
Abstract:
G.729.1 is an 8-32 kbps scalable
wideband speech and audio codec interoperable with G.729, G.729A and G.729B.
It, however, requires much more computation than its narrowband coders. In this
talk, hardware IPs for accelerating the peformance of the G.729.1 will be
presented. The IPs are implemented on an embedded FPGA
platform, where a soft processor works with them, resulting in a significant
performance improvement.
5. A Platform-Based
Approach to Realizing High Performance DSP Subsystems in FPGAs
Speaker:
Abstract:
FPGAs
have become key components in implementing high performance DSP systems,
especially in the areas of digital communications, video, and image
processing. The compute/memory bandwidth
of a modern FPGA far exceeds that of a microprocessor or DSP processor running
at clock rates two to ten times that of the FPGA, and with their capability for
realizing highly parallel arithmetic micro-architectures, FPGAs are ideally
suited for creating custom data path processors. Despite these characteristics, FPGAs have not
been broadly adopted in the DSP community because traditional programming
models are based around hardware description languages (HDLs) like VHDL and
Verilog, and electronic design automation tools that are foreign to most signal
processing engineers.
In
the recent years, a number of commercial design tools have made strides in
bridging the gap between the C programming language and HDLs, and between the
MATLAB / Simulink environment (The Mathworks, Inc.) and HDLs and
hardware-centric intellectual property (IP) libraries especially targeting
FPGAs. This presentation describes a
platform-based approach to realizing DSP systems in FPGAs that combines
algorithm-centric programming models, high-level modeling environments,
automatic code generation, standard hardware platforms, and embedded
software. We demonstrate ways in which
the platform provides descriptive expressiveness, fine-grained control of
hardware architecture, and faithful simulation semantics from a system level
environment. With interfaces and
abstractions to implement data paths, control, and embedded software, each in a
language suited to a particular function, and with heterogeneous simulation semantics
and deployment, this platform enables a DSP design team to target FPGAs with
less FPGA-specific expertise than ever before possible.
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Webpage last modified: Jan 8, 2009