As process technologies migrate to 130nm and below, new defect types are raising concerns about the quality and effectiveness of manufacturing test. This session will discuss what you can do to ensure high quality test without jeopardizing schedules or budget. Topics include testing for at-speed and bridging defects, test compression, and embedded memory test.

Kathy Yang, Applications Engineer Consultant at Mentor Graphics Ottawa, received the M.Sc. degree in computer science and application from University of Science and Technology of China, HeFei, China in 1997, and BS in Electronic information and engineering from Xi'An JiaoTong University, Xi'An, China in 1990.

Kathy Yang jointed Mentor Graphics BeiJing, China in 1997, and then Mentor Graphics Canada in 2000. From 1993 to 1997, she was an ASIC design/verification and DFT engineer for microprocessor projects, and a computer system integration engineer in both hardware and software area from 1990 to 1993.

Kathy has performed contract work and has been a consultant to several companies in the area of Design-for-Test as the applications engineer at Mentor Graphics. She supports Mentor's whole suite of Design-for-test tools including: internal scan insertion, ATPG, memory built-in self-test, boundary scan insertion, and logic built-in self-test. She also supports Mentor's hardware simulation, and Software/Hardware co-verification solution.