From the late 90's to the present, we have seen a surge in the data rate of CMOS input/output (I/O) interfaces. Data rates around 2-3Gb/s are now common, and 10Gb/s CMOS transceivers are commercially available.

This presentation has three parts. It begins with an overview of the past I/O performance trends, highlighting the challenge of the bandwidth bottleneck, which the presenter believes is the driving force behind the emergence of the CMOS high-speed IOs. Next, architecture- and circuit-level solutions to the bandwidth bottleneck will be presented, with an emphasis on multi-bit, multi-port high-speed I/Os. Finally, the presentation provides an analysis and discussion of future trends, and the speed limitation of CMOS high-speed I/Os.

Dr. Hirotaka Tamura received his Ph.D., M.Sc. and B.Sc. degrees in electronics from Tokyo University in 1982, 1977, and 1977 respectively. In 1982, he joined Fujitsu Laboratories LTD., and engaged in the development of exploratory devices including Josephson junction devices, high-temperature superconductor devices, and quantum-effect devices. He moved into the field of CMOS circuit design in 1995, and started working on CMOS high-speed signaling in 1996. His current research interests include the architecture and transistor-level implementation of circuits for high-speed CMOS I/Os.