Seminar Announcement
These events are organized by various sub-sets of the IEEE Toronto Section.
The contact person listed below is the volunteer who has arranged this event.
Please use the e-mail link provided if you have any questions, suggestions,
or concerns.
| Title
|
Key Enabling Technologies for 3D IC Integration and SiP
an IEEE Components, Packaging and
Manufacturing Technology Society
Distinguished Lecture |
| Speaker
|
Prof. John H. Lau
Hong Kong University Science & Technology |
| Day and Time
|
Wednesday, September 23, 2009, 11:00 a.m. |
| Location
|
Room GB 120, Galbraith Building
University of Toronto
35 St. George Street
map - select GB |
| Organizer
|
IEEE Circuits & Devices Chapter |
| Contact
|
Emanuel Istrate, E-mail:
All are welcome. Refreshments will be served. |
| Abstract |
Moore's law has been the most powerful driver for the development of
the microelectronic industry. This law emphasizes on lithography
scaling and integration (in 2D) of all functions on a single chip,
perhaps through system-on-chip (SoC). On the other hand, the
integration of all these functions can be achieved through system-in-
package (SiP) or, ultimately, 3D IC integration, which is a very
complicated subject. It involves component and system designs, FAB,
packaging, testing, and materials and equipment suppliers. The key
enabling technologies for 3D IC integration and wafer-level Packaging
(WLP) are, e.g., electrical, optical, thermal, and mechanical designs
and tests, known good die (KGD), TSV (through silicon vias) with RDL
(redistribution layers), wafer thinning and thin wafer handling, thin
chip strength measurement and improving, microbump forming and
assembly, low temperature C2W and W2W bonding, embedded WLP, hybrid
SiP, optical PCB, and thermal management. In this lecture, all these
enabling technologies will be discussed. Most of the materials are
based on the technical papers published within the past 3 years by the
instructor and others.
|
| Biography |
John Lau has been a visiting professor at HKUST (Hong Kong University
Science & Technology) since January 2009. Prior to that, he was the
Director of Microsystems, Modules & Components (MMC) Laboratory with
Institute of Microelectronics (IME, Singapore) for 2 years and a
Senior Scientist/MTS at HP/Agilent in California for more than 20
years. With more than 30 years of R&D and manufacturing experience, he
has authored or co-authored more than 300 peer-reviewed technical
publications and more than 100 book chapters, and given more than 250
presentations. He has authored and co-authored 16 textbooks on
advanced packaging, solder joint reliability, and lead-free soldering
and manufacturing. John earned his Ph.D. degree in theoretical and
applied mechanics (University of Illinois) and three M.S. degrees in
structural engineering, engineering physics and management science in
North America. He is an elected ASME Fellow and has been an IEEE
Fellow since 1994.
|
|