IPFA 2012
Marina Bay Sands Singapore
2 - 6 July 2012

Speaker: Dr. Dave VALLETT, IBM, Essex Junction, VT

Title: Fault Isolation Techniques for Package and Die Level Failure Analysis

Abstract: Microelectronic and now nanoelectronic fault isolation has become increasingly challenging with higher density packaging, transistor counts into the billions, scaling below 32 nanometers, and new materials. This course examines both traditional and recently developed tools and techniques for isolating faults on simple and advanced IC packages and chips. Methods for AC and DC parametric, memory, and logic failures are discussed. Electrical, thermal, magnetic, electron and ion beam, and photonic techniques are presented, including: stuck-fault diagnostics, time domain reflectometry, magnetic current imaging, OBIRCH/TIVA, static and time-resolved emission, laser voltage probing, thermography, tunnelling AFM and AFP, and many others. The challenges of non-invasive probing and characterization of ‘non-visual defects’ are also covered. Case histories will be shown and capabilities and limitations examined.

Upon completion students will be able to state the purpose and benefits of fault isolation; determine prerequisites like characterization and sample preparation; examine trade-offs between methods for various fail modes and sample form-factors; describe tools and techniques and the physical and electrical principles behind them; decide which methods to use; and identify strengths and limitations of specific techniques.

The tutorial will benefit test and debug personnel; failure analysts; characterization, yield, and reliability engineers and managers; and anyone who submits devices to, performs, or analyzes results from failure analysis laboratories. Researchers, developers, and vendors of fault isolation and related equipment and failure analysis tooling in general will also benefit.

Speaker’s Biography: David Vallett has almost 30 years experience in CMOS characterization and failure analysis. He is with the Technology Quality Analytical Services organization in IBM’s Systems and Technology Group where he manages the department responsible for technology reliability and packaging failure analysis and fault isolation. He holds fourteen US patents and shared in IBM's Outstanding Technical Achievement award for his contributions to picosecond imaging circuit analysis (PICA) using time-resolved photon emission microscopy. Mr. Vallett is a senior member of the IEEE, a member of the Electronic Device Failure Analysis Society board of directors, and belongs to Tau Beta Pi - the National Engineering Honor Society. He is a past chair of the International SEMATECH Product Analysis Forum and was selected as the 2008 General Chair for ISTFA - the International Symposium for Testing and Failure Analysis. Mr. Vallett holds the BS degree in electrical engineering from the University at Buffalo, New York, USA.