Past and Future of Integrated Circuits Technology

Prof. Hiroshi Iwai

Frontier Research Center, ex-president of EDS

Tokyo Institute of Technology, Japan

Date: Tuesday, 5th May

Time:4:00p,

Location:C14, Sackville Street Building

Abstract

The development of the integrated circuits has been accomplished with the downscaling of transistors (MOSFETs). We are now able to integrate millions of CMOS transistors in the nanoscale in a silicon chip with few centimeters square. The CMOS integrated circuits as well as their core device technology are expected to evolve further for at least a couple of decades and their importance will be further increased in future intelligent society.
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference.  However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits. This talk reviews the challenges of past and future CMOS downsizing and its manufacturing. Then, possible limitation for the downscaling is discussed. Finally, possible technology development after reaching the downscaling limit is explained.

Hiroshi Iwai is a professor in Frontier Collaborative Research Center and also in Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology.  He received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo. He worked in the research and development of integrated circuit technology in Toshiba for 26 years, and Tokyo Institute of Technology for 10 years. His current research fields are for Nano-CMOS technology in general, including those of high–k and metal gate stack, plasma doping for ultra-shallow junctions, Ni salicide, Metal S/D, Si-nanowire MOSFET, and Ge and III-V MOSFETs, He has authored and coauthored more than 600 papers.