JAPAN IMC/IEMT April 1998 HighLights
The International Microelectronics Conference (Sponsored by IMPAS JAPAN) and the International Electronic Manufacturing Technology (sponsored by IEEE CPMT JAPAN) joint symposium was held on April 15-17. The Technical sessions focused on thermal management, reliability, optical components, substrate, component, materials, MCM, BGA, CSP and flip-chip. I was a presenter in the symposium. The following is the minutes.
"Electronic Packaging Research and Education in the 21st Century at PRC" - Rao R Tummala, Georgia Institute of Technology, USA
Next generation of packaging must be consistent with both semiconductors and systems. The packages in the past have been mostly passive containers for semiconductors. Given the needs for extremely compact and ultra low-cost electronic systems of the 21st century and given the wafer fabrication costs that are $3-5 B a plant, what should packaging be in the 21st century ? Any packaging technology should also be built upon the learning of current state-of-the-art packaging. Highly integrated and low cost packaging as a single level and single component that is capable of improving performance, reducing cost and size of 10X in each is proposed. Similar advances are also proposed in electronic packaging education for 21st century introducing packaging at pre-college level and providing a system-level view at undergraduate and graduate levels.
"Fuzzy Logic Based Thermal Design for MCM Placement" - Yu-Jung Huang, I-Shou University, Taiwan
The force-directed algorithm was modified based on the fuzzy set theory. After formulating the force equations based on the power dissipation values of the individual bare chip, a set of simultaneous equations can be solved to determine equilibrium locations for the fuzzy thermal placement.
"The Application of Flip Chip Bonding Technology Using Anisotropic Conductive Film on the Mobile Communications Terminals" - Akimbo Torii, Toshiba Corporation, Japan
Flip Chip Bonding (FCB) technology has been developed using gold ball bumps and anisotropic conductive films (ACF). The mass production technology has been developed with full automatic bonding machines. The FCB technology was applied for the liquid crystal display (LCD) module used in pagers which is one of the mobile communications terminals.
"A Study of New Flip Chip Packaging Process for Diversified Bump and Land Combination" - Hiroshi Noro, Nitto Denko Corporation, Japan
A flip chip packaging technology using nonconductive underfill resin sheet has been developed. Underfill sheet is laminated onto substrate. The bumped die is subsequently attached onto substrate which is covered with underfill
sheet under proper heat and pressure.
"A Roadmap to Low Cost Flip Chip and CSP using Electroless Ni/Au" - T.Oppert, Pac Tech, Germany
Electroless Ni/Au bumps offer a powerful roadmap for flip chip interconnections on board (FCOB) and in package (FCIP) in the next millennium. The main challenges of electroless Ni/Au as an under bump metallization is the reduction of pitch to 50um and the development of solder application techniques.
-- Submitted by Masazumi Amai
"A Compact Modeling Approach Using a Genetic Algorithm for Accurate Thermal Simulation " - Toshihiko Nishio, IBM Japan.
Although the LSI component modeling method was proposed by DELPHI, a genetic algorithm was proposed by them. Their model was applied for the notebook PC keyboard thermal simulation.

"Worldwide Packaging Trends for portable products" - Thomas Goodman, TechSearch Int., USA

Type Mounting Device I/O Pitch (mm) Maker
--------- --------------- ---------------- ----- ---------- -----------
Notebook, TCP, QFP Pentium 320 0.25 IBM Jpn
Module Pentium, etc, Gateway
BGA Chip set
PGA,QFP Pentium, chip set 296 Canon
CSP DRAM 28 0.8 Daewoo
Sunnote FC-MSP DSP 344 IBM Japan
book FC-MSP Graphic 240 NEC
ROM 44
FC-MSP Pentium, chip set Fujitsu
PDA FC-CSP CPU, I/F 221,284 1.0 Panasonic
BGA CPU Fujitsu
Flip chip uContr, G/A Casio
Memory, ect
QFP,BGA CPU, ASIC Cassiopeia
Card PC FC-CSP u Proc., I/O 216-280 PFU
CSP Pentium,DRAM 240,40 0.8,0.5
Cell Computer
Cell Phones Flip chip Processor 130, Motorola
CSP DSP, CPU, flash 32-100, 0.8, 1.0 Sony
CSP ASIC, DSP, flash 28-144, 0.8, 1.0 Sharp
Digital CSP ASIC 176 0.8 Sharp
Camcorder FC-CSP 44-208 0.5 Sony
FC-CSP 79-252 0.8 JVC
Digital QFP (SOP) RISC CPU, ASIC Olmpus
Camera QFP, SOP Ricoh
Palm-Top COB 8-Bit uControl Tamagotchi Game

"Flip Chip Bonding Reliability of Advanced Glass Ceramic Chip Size Packages " - Ichiro Hazeyama, NEC Corporation, Japan
NEC has developed Glass Ceramic CSP. The 64M DRAM chip was connected to the glass ceramic substrate via Au bumps by flip chip bonding technique.

"Reliability of Solder Joints in CSPs of Various Designs and Mounting Conditions" - Masato Sumikawa, Sharp Corporation, Japan
BLR (125/-40C)
IR Reflow Stencil 5 min ramp/25min dwell
Peak Thickness PCB Pad Initial Failure
--------- ---------- --------- -----------------------
230 C 0.15 mm Cu 900 cys
Au/Ni/Cu 600 cys
210 C 0.15 mm Cu 600 cys
Au/Ni/Cu 300 cys
250 C 0.15 mm Cu 900 cys
Au/Ni/Cu 600 cys
230 C 0.10 mm Cu 500 cys
230 C 0.18 mm Cu 900 cys

Package ; Similar to u*BGA, Solder ; 63/37
Size; 12x12 mm (176 pins)

"Reliability Study of the Laminate-Based Flip-Chip CSP" - Yushi Matsuda, Motorola Japan, Japan

The Just About Chip Size Package (JACS-Pak) design has been developed for portable product applications. This paper focused on BLR.
BLR (-55/125, 5.8 cys/Hour)
------------- ------------ -------- --------------------
JACS (FC-CSP) 0.5 mm pitch 88 I/O 1400 - 1500
OMPAC 1.5 mm pitch 68 I/O 1100 - 1200
Glob top BGA 1.0 mm pitch 196 I/O 1900 - 2000

"New Flip Chip Attach Technology for Fine Pitch Interconnections Using Electroplated Copper Bumps formed on a Substrate " - Fumitake Ueno, Toshiba Corporation, Japan
Electroplated copper bump flip chip technology has been developed. The contact resistance change after thermal cycling tests and THS was small.
, TC-9 Japan Interface
amai@ti.com -- masazumi