The Fourth VLSI Packaging Workshop of Japan
Kyoto Kokusai Hotel, Kyoto, Japan --- November 30 - December 2, 1998
The IEEE CPMT Society and the National Institute for Standards and Technology are jointly sponsoring the Fourth VLSI Packaging workshop of Japan. The workshop serves the growing need of our Information-Oriented Society which is becoming more reliant on "Mobile Communication", "Personal Computing", and "Computer Networks". These systems require faster and higher-performance microelectronics devices, which are more dependent on packaging technology. As a result, this workshop focuses on the packaging technologies such as BGA, CSP, Flip-chip, MCM and bare-chip packaging and their applications.
All attendees are expected to be specialists in the fields and participate in discussions. The Workshop[ will be held in English and conducted in a single session. Each oral presentation will be allowed 30 minutes including 10 for discussion. Papers on new developments in the following areas are expected (please Fax first to see if there are still openings for your paper):
Overlapping Boundaries of VLSI and System Packaging
Network and Mobile Computing Packaging
Audio, Video, Games, and Digital Camera Applications
Area Array Packaging: BGA and CSP
Low cost MCM and KGD
Build-up PCB, ACF, and Flip-chip connection
Concurrent Engineering for Design and Manufacturing
Electrical/Thermal/Mechanical Modeling and Characterization
New Materials and Processing
Reliability Physics and Environmental Issues
For rules of submission please contact Fuminori Ishitsuka at email <ishi@ilab.ntt.co.jp>, Fax: +81 422 59 2593, Phone: +81 422 59 2539. For final program contact George Harman at <george.harman@nist.gov>. Authors of selected papers will be notified by July 30, 1998.