A Physics-of-Failure Approach for Accelerated Product Qualification and Quality Assurance
October 12, 1998
Marriott Inner Harbor, Baltimore, MD
Cost: Contact Dr. Abhijit Dasgupta or Juanita Mendoza, jm274@calce.umd.edu --- CALCE program
Overview:
Are you spending too much time and money in accelerated testing to improve the integrity of your products? Does your testing give you quantitative information about in-service reliability? Does your test program provide information for designers and manufacturers to proactively build-in reliability and quality into future products?
The physics-of-failure (PoF) approach provides a verifiable way to accelerate product maturity cost-effectively, and tailored accelerated stress testing is one of the key resources in the PoF approach. Accelerated stress exposures can be used to simulate compressed life-cycles, to evaluate potential failure mechanisms. If done early in the development phase, in conjunction with PoF design, stress tests can accelerate process and design maturity, and enable early introduction of products with robust stress margins. Accelerated stress exposures are also useful as a stress screen in the production phase, to stimulate and precipitate latent defects that could cause infant mortality in the field. Proper PoF-based use of accelerated
stress tests results in cost savings, time savings and quality
improvements, which are orders of magnitude better than those attained using traditional empirical approaches.
Learn the latest techniques for making accelerated stress testing a value-added activity. Hear how industry leaders are using accelerated test results to take pro-active corrective action early in the design and production phases for ensuring consistently high integrity of design and process. See the latest web-based tools to facilitate the job of integrating PoF approaches into the product qualification and quality assurance process.
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CALCE Consortium Fall Research Review and Planning Meetings: October 13-15 1998
Marriott Inner Harbor, Baltimore, MD
Contact: Joan Lee (ph. 301-405-5323, fax: 301-314-9269)
joanyuan@eng.umd.edu
Overview:
On October 13-15, 1998, the CALCE Consortium will present its end of year research results in its Research Review and Planning Meetings at Marriott Inner Harbor, Baltimore, Maryland. Presentations will cover the over $4M of research being conducted in the following topics.
Portions of those meetings are open to invited non-members. This is a University of Maryland Foundation Event.
Tentative Agenda: Tuesday, October 13, 1998
8:05 State of the Consortium
8:45 Status of Research Activities
Reliability of Low-cost Flip Chip Assemblies
Assessment of Reliability of CSP Assemblies
Evaluation of Ion Diffusion Rate in Epoxy Molding Compounds
10:30 Status of Research Activities
Storage Testing Using Mixed Flowing Gases
Moisture Permeation Through Inorganic Coatings
Non-Adhesion of Mold Compound and the Reliability Effect on Wire Bond Shear Strength
Suitability of PEMs for Fast Jet Avionics
Accelerated Testing of PEMs for Long Term Storage
Combustion of Electrically Degraded PEMs
1:00 Status of Research Activities
Assessing and Mitigating Risks in Complex Electronic Systems
Parts Quality and Integrity Assessment
Technology Specific Protocols for Uprating
Performance Derating as An Alternative to Uprating
Legal Implications of Part Use Beyond the Manufacturers' Specified Range
Tentative Agenda: Wednesday, October 14, 1998
8:05 Status of Research Activities
Web-based Interactive Guidelines for Physics-of-Failure Approach to Accelerated Testing
Verification of PoF-based Acceleration Transforms for Circuit Card Assemblies
Extention of PoF Accelerated Testing Approach to Electronic Boxes
Physics of Failure Strategies for Screening of Electronic Assemblies
10:30 Status of Research Activities
Qualified Manufacturing Process and Design Guidelines for Insulated Metal Circuit Boards
Validation of Semi-Analytic Fatigue Failure Models
New MDRR Interconnect Fatigue Models
1:00 Status of Research Activities
Conductive Filament Formation Modeling in Low- voltage/Fine-line PWBs
Fabrication and Performance of Compact Thermosyphons Using Microfabricated Components
Failure Mechanisms in Cathode Ray Tubes
Health Monitoring of Electronic Systems
Introduction to Integral, Embedded and Buried Passives
Rapid Processing of Liquid Encapsulants Using Variable Frequency Microwave Energy
Analysis of Cannot Duplicate (CND) Failures
Effect of Moisture on Corrosion Rates and Reliability of PWB
Metallization Systems
Moisture Related Growth Failure Mechanisms of Assemblies
-- submitted by Joan Lee, CALCE
4th VLSI Packaging Workshop of Japan in Kyoto
Advanced Program
Contact: George Harmon 301 975 2097
Monday, November 30
10:00 – 12:00 Keynote Speakers
R. Otsuka, Prof. Liu & others
1:00 – 3:00
CSP/Bare Chip Packaging Chairs: Okada, Mizumoto
"A Robust and Low Cost Stack Chips Package"
by D. H. Kim, S. J. Cho (Hyundai Electronics Industries)
"High Quality Small Package Development by Flip Chip Method" by Y. Egawa, Y. Shiraishi, S. Ohuchi, and Y. Kohara (Oki Electric Industry Co.)
"A Flip-chip BGA with Organic Substrate for High Performance Devices" by M. Wtanabe, S. Baba, Y Tomita, H. Matsusima (Mitsubishi)
"Flip-chip CSP using a Double Layered ALIVH Substrate"
by T. Tomura, S. Yuhaku, M. Itagaki, Y. Bessho, K. Eda, M. Tsukamoto and T. Ishida (Matsusita)
3:30– 5:30
Electrical Characterization Chairs: Ishizuka, Schaper
"A high-effective PCB simulator including ICs characteristics"
by H. Kimura (NTT)
"An Algorithm for Sensitivity Analysis of Electrical Performance Parameters" by C. Jiao, J. L. Prince, A. Yaghmour and A. C. Cangellaris (University of Arizona, University of Illinois, IBM, Hitachi Cable Co.)
Tuesday, December 1
8:50 – 10:20
Packaging Trend, Chair Hirata
"US SIA Packaging Roadmap and Challenged"
by R. Werner and C.S. Chan (SEMATECH Inc.)
"Worldwide Market Trends in Area Array Packaging"
by E. Jan Vardaman (TechSearch International, Inc.)
10:30 – 12:30
Electrical Characterization Chairs: Sudo, Prince
"A New RLC Modeling Tool Based on the Partial Element Equivalent Circuit (PEEC) technique"
by S. Hasan, A. Cangellaris, and J. Prince
(University of Arizona, University of Illinois)
"Relation Between Radioted Emissions"
by S. Shirkawa (Hitachi)
"Signal Propagation on Seamless High Off-chip Connectivity (SHOCC) Interconnects" by L. W. Schaper, S. Afonso, W.D. Brown, and J.P. Parkerson (University of Arkansas)
"Compact Liquid-cooling System for High-Speed Switching MCMs" by K. Okazaki, N. Yamanaka, A. Harada, S. Sasaki, and T. Kishimoto (NTT)
1:30 – 3:00
Panel Discussion Members: Nakamura Sudo, Ishizuka, Len Shaper, John Prince, Otuka
"Requirement of Electrical Performance for Future Packaging Materials"
--Which is better, large ƒÃ or not, large tan ƒÃ or not, more fine pitch or not, more consideration skin effect or not, more fine pitch or not.
3:30 – 5:00
Reliability: Chairs: Ohara, Liu
"Evaluation of Barrier Metals of Sn-Ag Solder Bumps for Flip-chip Interconnection"
by S. Honma, M. Miyata, H. Aoki, and Y. Hiruta (Toshiba)
"High Resolution Deformation Measurement on CSP and Flip Chip", by Dietmar Vogel, Jurgen Simon, Andreas Schubert, Bernd Michel (Fraunhofer Institute of Reliability and Microinte gration, IZM)
5:00 – 9:00
Materials: Chairs: Kono, Harmer
"Thin Film Polymeric Materials in Microelectric Packaging and Interconnect: An Overview"
by P. Garrou (Dow Chemical USA)
"Development of 0.025 mm pitch Anisotropic Conductive Film" by F. Eriguch, Y. Hotta, M. Yamaguchi, M. Maeda and F. Asai (Nitto Denko)
"Anisotropic Conductive Paste (ACP) available for Flip Chip"
by Minoru Hara (Toshiba Chemical Co.)
Wednesday, December 2
Materials Chairs: Kamehara, Garrou
8:50 – 10:20
"Development of a Bumped Tape Carrier (BTC) for CSP Substrate" by T. Asada and T. Amano (Furukawa Denko)
"High-density Build-up Packaging Substrate for High-pin-count Area array Interconnections"
by T. Shimoto, K. Matsui, Y. Shimada, and K. Utsumi (NEC)
"An Adhesive for Tapa Ball Grid Array Packages"
by Y. Takigawa and E. Yano (Fujitsu)
10:40 – 12:10
CSP/Bare Chip Packaging chairs: Mimura, Waldaman
"Development of MITSUBISHI Mold CSP"
by S. Yamada, M. Yasunaga, K. Harada, Y. Takemoto, K. Misumi, Y. Takata, A. Yamazaki, A Sawai, M Hisahara, K. Imamura, Y. Noguchi and Y. Hirata (Mitsubishi Denki)
"Development of SMAAP (super mold area array package)"
by M. Suwa, M. Onodera, S. Nakaseko, and T. Kawahara (Fujitsu)
"Real CSP", Oki Denki