The Fourth VLSI Packaging Workshop of Japan
Kyoto Kokusai Hotel, Kyoto, Japan --- November 30 - December 2, 1998

The IEEE CPMT Society and the National Institute for Standards and Technology are jointly sponsoring the Fourth VLSI Packaging workshop of Japan. The workshop serves the growing need of our Information-Oriented Society which is becoming more reliant on "Mobile Communication", "Personal Computing", and "Computer Networks". These systems require faster and higher-performance microelectronics devices, which are more dependent on packaging technology. As a result, this workshop focuses on the packaging technologies such as BGA, CSP, Flip-chip, MCM and bare-chip packaging and their applications.
All attendees are expected to be specialists in the fields and participate in discussions. The Workshop will be held in English and conducted in a single session. Each oral presentation will be allowed 30 minutes including 10 for discussion. Papers on new developments in the following areas are expected :
Overlapping Boundaries of VLSI and System Packaging
Network and Mobile Computing Packaging
Audio, Video, Games, and Digital Camera Applications
Area Array Packaging: BGA and CSP
Low cost MCM and KGD
Build-up PCB, ACF, and Flip-chip connection
Concurrent Engineering for Design and Manufacturing
Electrical/Thermal/Mechanical Modeling and Characterization
New Materials and Processing
Reliability Physics and Environmental Issues
For final program contact George Harman at <george.harman@nist.gov>.

Preliminary Program and Chair

Monday, November 30

10:00 – 12:00 Keynote Speakers R. Otsuka, Prof. Liu & others

1:00 – 3:00
CSP/Bare Chip Packaging (1) Okada, Mizumoto
"A Robust and Low Cost Stack Chips Package"
by D. H. Kim, S. J. Cho (Hyundai Electronics Industries)
"High Quality Small Package Development by Flip Chip Method"
by Y. Egawa, Y. Shiraishi, S. Ohuchi, and Y. Kohara (Oki Electric Industry Co.)
"A Flip-chip BGA with Organic Substrate for High Performance Devices"
by M. Wtanabe, S. Baba, Y Tomita, H. Matsusima (Mitsubisi)
"Flip-chip CSP using a Double Layered ALIVH Substrate"
by T. Tomura, S. Yuhaku, M. Itagaki, Y. Bessho, K. Eda, M. Tsukamoto and T. Ishida
(Matsusita)
3:30– 5:30
Electrical Characterization (1) Ishizuka, Schaper
"A high-effective PCB simulator including ICs characteristics"
by H. Kimura (NTT)
" An Algorithm for Sensitivity Analysis of Electrical Performance Parameters"
by C. Jiao, J. L. Prince, A. Yaghmour and A. C. Cangellaris
(University of Arizona, University of Illinois, IBM, Hitachi Cable Co.)

Tuesday, December 1

8:50 – 10:20
Packaging Trend Hirata
"US SIA Packaging Roadmap and Challenged"
by R. Werner and C.S. Chan (SEMATECH Inc.)
"Worldwide Market Trends in Area Array Packaging"
by E. Jan Vardaman (TechSearch International, Inc.)
10:30 – 12:30
Electrical Characterization (2) Sudo, Prince
"A New RLC Modeling Tool Based on the Partial Element Equivalent Circuit (PEEC) technique"
by S. Hasan, A. Cangellaris, and J. Prince
(University of Arizona, University of Illinois)
"Relation Between Radioted Emissions"
by S. Shirkawa (Hitachi)
"Signal Propagation on Seamless High Off-chip Connectivity (SHOCC) Interconnects"
by L. W. Schaper, S. Afonso, W.D. Brown, and J.P. Parkerson (University of Arkansas)
"Compact Liquid-cooling System for High-Speed Switching MCMs"
by K. Okazaki, N. Yamanaka, A. Harada, S. Sasaki, and T. Kishimoto (NTT)
1:30 – 3:00
Panel Discussion Nakamura
Sudo, Ishizuka, Len Shaper, John Prince, Otuka
"Requirement of Electrical Performance for Future Packaging Materials"
--Which is better, large ƒÃ or not, large tan ƒÃ or not, more fine pitch or not, more consideration skin effect or not, more fine pitch or not
3:30 – 5:00
Reliability Ohara, Liu
"Evaluation of Barrier Metals of Sn-Ag Solder Bumps for Flip-chip Interconnection"
by S. Honma, M. Miyata, H. Aoki, and Y. Hiruta (Toshiba)
"High Resolution Deformation Measurement on CSP and Flip Chip"
by Dietmar Vogel, Jurgen Simon, Andreas Schubert, Bernd Michel (Fraunhofer Institute of Reliability and Microinte gration, IZM)
5:00 – 9:00
Material (1) Kono, Harmer
"Thin Film Polymeric Materials in Microelectric Packaging and Interconnect: An Overview"
by P. Garrou (Dow Chemical USA)
"Development of 0.025 mm pitch Anisotropic Conductive Film"
by F. Eriguch, Y. Hotta, M. Yamaguchi, M. Maeda and F. Asai (Nitto Denko)
"Anisotropic Conductive Paste (ACP) available for Flip Chip"
by Minoru Hara (Toshiba Chemical Co.)

Wednesday, December 2

Materials Kamehara, Garrou
8:50 – 10:20
"Development of a Bumped Tape Carrier (BTC) for CSP Substrate"
by T. Asada and T. Amano (Furukawa Denko)
"High-density Build-up Packaging Substrate for High-pin-count Area array Interconnections"
by T. Shimoto, K. Matsui, Y. Shimada, and K. Utsumi (NEC)
"An Adhesive for Tapa Ball Grid Array Packages"
by Y. Takigawa and E. Yano (Fujitsu)
10:40 – 12:10
CSP/Bare Chip Packaging (2) Mimura, Waldaman
"Development of MITSUBISHI Mold CSP"
By S. Yamada, M. Yasunaga, K. Harada, Y. Takemoto, K. Misumi, Y. Takata, A. Yamazaki, A Sawai, M Hisahara, K. Imamura, Y. Noguchi and Y. Hirata (Mitsubishi Denki)
"Development of SMAAP (super mold area array package)"
by M. Suwa, M. Onodera, S. Nakaseko, and T. Kawahara (Fujitsu)
Real CSP, Oki Denki

Send requests for further information, and registration forms, to the following address by mail, FAX, or email (email is preferred):